Parallel Peripheral Interface (PPI)
1-20
ADSP-BF526 EZ-Board Evaluation System Manual
By default, the EZ-Board boots from the 16-bit flash parallel memory. SPI
flash can be selected as the boot source by setting the boot mode select
switch (
SW1
) to position 3 (see
“Boot Mode Select Switch (SW1)” on
Parallel Peripheral Interface (PPI)
The ADSP-BF526 processor provides a parallel peripheral interface (PPI),
supporting data widths up to 16 bits. The PPI interface provides three
multiplexed frame syncs, a dedicated clock input, and 16 data lines. The
full PPI port is accessible on the expansion interface II connector (
P3
).
The PPI signals connect to multi-function pins; the upper eight data bit
signals are configured for the rotary, SPI,
UART1
, and
LED0
interfaces. To
use the upper eight PPI data lines at connector
P3
, change the board as fol-
lows: disable rotary switch (
SW13
positions 1–3
OFF
) and disable the
UART1
interface (remove a jumper from
JP3
).
LED0
mimics the
PPID8
data pin.
The PPI has a dedicated clock, generated from the expansion interface II.
The PPI is not used on the EZ-Board, intended for use on the expansion
interface II.
Rotary Encoder Interface
The ADSP-BF526 processor has a built-in, up-down counter with support
for a rotary encoder. The three-wire rotary encoder interface connects to
the thumbwheel rotary switch (
SW13
) and expansion interface II connector
(
P3
). The rotary encoder can be turned clockwise for the up function,
counter clockwise for the down function, or can be pushed towards the
center of the board to clear the counter.
The rotary switch is a two-bit quadrature (gray code) counter with a
detent, meaning that both the down signal (
CDG
) and up signal (
CUD
)
