ADSP-BF526 EZ-Board Evaluation System Manual
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Using The ADSP-BF526 EZ-Board
Land Grid Array
The ADSP-BF526 EZ-Board has provisions for probing every port pin
and the EBIU interface of the processor on connectors
P5
,
P6
, and
P7
. The
connector locations are intended for use with a Tektronix DMAX logic
analyzer connector, but can be probed with any oscilloscope or logic ana-
lyzer. Connectors
P5
and
P6
require the primary retention posts, while
connector
P7
can use either the primary or secondary retention post. For
pinout information, refer to
“ADSP-BF526 EZ-Board Schematic” on
For more information on the Tektronix DMAX logic analyzer interface,
go to the Tektronix Web site.
Expansion Interface II
The expansion interface II allows an Analog Devices EZ-Extender
®
or a
custom-design daughter board to be tested across various hardware plat-
forms that have the same expansion interface.
The expansion interface II implemented on the ADSP-BF526 EZ-Board
consists of four connectors, three of which are 0.1 in. shrouded headers
(
P2—4
) and the last of which is a Samtec QMS series header (
J1
). The con-
nectors contain a majority of the ADSP-BF526 processor signals. For the
pinout of the connectors, go to
“ADSP-BF526 EZ-Board Schematic” on
. The mechanical dimensions of the expansion connectors can be
obtained by contacting
.
For more information about daughter boards, visit the Analog Devices
Web site at:
http://www.analog.com/processors/tools/blackfin
Limits to current and interface speed must be taken into consideration
when using the expansion interface II. Current for the expansion interface
II is sourced from the EZ-Board, therefore, the current should be limited
to 1A for 5V and 500 mA for the 1.8V planes. When a battery supplies
