ADE9000 Technical Reference Manual
UG-1098
Rev. 0 | Page 41 of 86
Example 1: Fixed Data Rate Data, Seven Channel Samples
WFB_CAP_SEL = 1, WF_IN_EN = 1, and BURST_CHAN = 0000
in the WFB_CFG register indicates that there is fixed data rate
data in the waveform buffer and the user wants to read out
samples from all seven channels. A command is sent to read
Address 0x801, which is interpreted as a read to the sample set
starting at Address 0x800. The first 32 SPI clocks return IA from
Address 0x800, followed by VA from Address 0x801, and so on,
until IN from Address 0x806. Then the sample set auto-increments
and the next data is IA from Address 0x808, followed by VA.
This example is shown in Figure 52. The default state of the
MOSI pin depends on the master SPI device; in Figure 52, it is
assumed to be high (Logic 1).
Example2: Resampled Data, Phase C (I and V samples)
WFB_CAP_SEL = 0 and BURST_CHAN = 0011 in the
WFB_CFG register indicates that there is resampled data in the
waveform buffer and the user wants to read out IC and VC
samples. A command is sent to read Address 0x801, which is
interpreted as a read to the sample set starting at Address 0x800.
VC waveform from Address 0x802 is first transferred, followed by
IC from Address 0x802. Then the sample set auto-increments
and the next data is VC from Address 0x806, followed by IC
from the same address, then VC from Address 0x80A and IC
from Address 0x80A, and so on (see Figure 53). The default
state of the MOSI pin depends on the master SPI device; in
Figure 53, it is assumed to be high (Logic 1).
Example 3: Fixed Data Rate Data, Single Address Read
Mode
WFB_CAP_SEL = 1 and BURST_CHAN = 1111 in the
WFB_CFG register indicates that there is fixed data rate data in
the waveform buffer and the user wants to read out one single
address. A command is sent to read Address 0x801, which is
interpreted as a read to Address 0x801. VA waveform from
Address 0x801 is transferred, followed by the CRC if
BURST_EN = 0. If BURST_EN = 1, the VA waveform data from
Address 0x801 is repeated again. This example is shown in
Figure 54. The default state of the MOSI pin depends on the
master SPI device; in Figure 54, it is assumed to be high
(Logic 1). The transfer of data continues as long as the CS line is
kept low and SCLK clocks arrive at the
SCLK pin.
Example 4: Resampled Data, Single Address Read Mode
WFB_CAP_SEL = 0 and BURST_CHAN = 1111 in the
WFB_CFG register indicates that there is resampled data in the
waveform buffer and the user wants to read out one single
address. A command is sent to read Address 0x801, which is
interpreted as a read to Address 0x801. The first 16 SPI clocks
return the VA waveform from Address 0x801, followed by the
IA waveform from Address 0x801, and finally the CRC if
BURST_EN = 0. If BURST_EN = 1, the VA and IA waveform
data from Address 0x801 is repeated again (see Figure 55).
SCLK
MOSI
CMD_HDR = 0x8018
MISO
IA AT 0x800, 32 BITS
SS
IA AT 0x808, 32 BITS
VA AT 0x801, 32 BITS IB AT 0x802,32 BITS
VB AT 0x803, 32 BITS
IN AT 0x806, 32 BITS
15523-
052
Figure 52. Waveform Buffer SPI Burst Read of Fixed Data Rate Samples, with BURST_CHAN = 0, to Read Out All Channels
SCLK
MOSI
MISO
SS
CMD_HDR = 0x8018
VC AT 0x802, 16 BITS
IC AT 0x802, 16 BITS
VC AT 0x806, 16 BITS
IC AT 0x806, 16 BITS
15523-
053
Figure 53. Waveform Buffer SPI Burst Read of Resampled Data, with BURST_CHAN = 0011, to Read out IC and VC Data
