Analog Devices ADE9000 Technical Reference Manual Download Page 60

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ADE9000 Technical Reference Manual

Rev. 0 | Page 60 of 86

Address

Name

Description

Reset

Access

0x387

CFVARHR_HI

Phase C accumulated fundamental reactive energy, MSB. Updated according to
the settings in the EP_CFG and EGY_TIME registers.

0x00000000

0x38F

CFVA_ACC

Phase C accumulated fundamental apparent power, updated after PWR_TIME
8 kSPS samples.

0x00000000

0x390

CFVAHR_LO

Phase C accumulated fundamental apparent energy, LSB. Updated according to
the settings in the EP_CFG and EGY_TIME registers.

0x00000000

0x391

CFVAHR_HI

Phase C accumulated fundamental apparent energy, MSB. Updated according to
the settings in the EP_CFG and EGY_TIME registers.

0x00000000

0x397

PWATT_ACC

Accumulated positive total active power, MSB, from AWATT, BWATT, and CWATT
registers, updated after PWR_TIME 8 kSPS samples.

0x00000000

0x39B

NWATT_ACC

Accumulated Negative total active power, MSB, from AWATT, BWATT, and CWATT
registers, updated after PWR_TIME 8 kSPS samples.

0x00000000

0x39F

PVAR_ACC

Accumulated positive total reactive power, MSB, from AVAR, BVAR, and CVAR
registers, updated after PWR_TIME 8 kSPS samples.

0x00000000

0x3A3

NVAR_ACC

Accumulated Negative total reactive power, MSB, from AVAR, BVAR, and CVAR
registers, updated after PWR_TIME 8 kSPS samples.

0x00000000

0x400

IPEAK

Current peak register.

0x00000000

0x401

VPEAK

Voltage peak register.

0x00000000

0x402

STATUS0

Status Register 0.

0x00000000

R/W

0x403

STATUS1

Status Register 1.

0x00000000

R/W

0x404

EVENT_STATUS

Event status register.

0x00000000

0x405

MASK0

Interrupt Enable Register 0.

0x00000000

R/W

0x406

MASK1

Interrupt Enable Register 1.

0x00000000

R/W

0x407

EVENT_MASK

Event enable register.

0x00000000

R/W

0x409

OILVL

Over current detection threshold level.

0x00FFFFFF

R/W

0x40A

OIA

Phase A overcurrent RMS½ value. If a phase is enabled, with the OC_ENA bit set

in the CONFIG3 register and AIRMSONE greater than the OILVL threshold, this
value is updated.

0x00000000

0x40B

OIB

Phase B overcurrent RMS½ value. If a phase is enabled, with the OC_ENB bit set

in the CONFIG3 register and BIRMSONE greater than the OILVL threshold, this
value is updated.

0x00000000

0x40C

OIC

Phase C overcurrent RMS½ value. If a phase is enabled, with the OC_ENC bit set

in the CONFIG3 register and CIRMSONE greater than the OILVL threshold, this
value is updated.

0x00000000

0x40D

OIN

Neutral current overcurrent RMS½ value. If enabled, with the OC_ENN bit set in

the CONFIG3 register and NIRMSONE greater than the OILVL threshold, this value
is updated.

0x00000000

0x40E

USER_PERIOD

User configured line period value used for resampling, fast RMS½ and 10 cycle rms/
12 cycle rms when the UPERIOD_SEL bit in the CONFIG2 register is set.

0x00500000

R/W

0x40F

VLEVEL

Register used in the algorithm that computes the fundamental active, reactive,
and apparent powers as well as the fundamental IRMS and VRMS values.

0x00045D45 R/W

0x410

DIP_LVL

Voltage RMS½ dip detection threshold level.

0x00000000

R/W

0x411

DIPA

Phase A voltage RMS½ value during a dip condition.

0x007FFFFF

0x412

DIPB

Phase B voltage RMS½ value during a dip condition.

0x007FFFFF

0x413

DIPC

Phase C voltage RMS½ value during a dip condition.

0x007FFFFF

0x414

SWELL_LVL

Voltage RMS½ swell detection threshold level.

0x00FFFFFF

R/W

0x415

SWELLA

Phase A voltage RMS½ value during a swell condition.

0x00000000

0x416

SWELLB

Phase B voltage RMS½ value during a swell condition.

0x00000000

0x417

SWELLC

Phase C voltage RMS½ value during a swell condition.

0x00000000

0x418

APERIOD

Line period on Phase A voltage.

0x00A00000 R

0x419

BPERIOD

Line period on Phase B voltage.

0x00A00000 R

0x41A

CPERIOD

Line period on Phase C voltage.

0x00A00000 R

0x41B

COM_PERIOD

Line period measurement on combined signal from Phase A, Phase B, and
Phase C voltages.

0x00A00000 R

0x41C

ACT_NL_LVL

No load threshold in the total and fundamental active power datapath.

0x0000FFFF

R/W

Summary of Contents for ADE9000

Page 1: ... data sheet FUNCTIONAL BLOCK DIAGRAM CF1 CF2 DIGITAL BLOCK SINC DECIMATION DSP ENGINE TOTAL AND FUNDAMENTAL IRMS VRMS ACTIVE REACTIVE APPARENT POWER AND ENERGY VTHD ITHD FREQUENCY PHASE ANGLE POWER FACTOR VPEAK IPEAK DIP SWELL OVERCURRENT FAST RMS 10 12 CYCLE RMS PHASE SEQ ERROR SAR TEMP SENSOR SPI INTERFACE CLKIN CLKOUT SCLK MISO MOSI CS GND IAP IAN VAP VAN ADC PGA ADC PGA ADE9000 ADC PGA ADC PGA...

Page 2: ...rotocol CRC 34 Additional Communication Verification Registers 34 CRC of Configuration Registers 35 Waveform Buffer 36 Fixed Data Rate Waveforms 36 Fixed Data Rate Waveforms Filling and Trigger Based Modes 37 Resampled Waveforms 39 Configuring the Waveform Buffer 40 Burst Read Waveform Buffer Samples from SPI 40 Interrupts EVENT 43 Interrupts IRQ0 and IRQ1 43 EVENT 43 Status Bits in Additional Reg...

Page 3: ...using a Rogowski coil current sensor The following conditions must be met for the input signals with gain 1 IAP IAN IBP IBN ICP ICN VAP VAN VBP VBN VCP and VCN 0 6 V peak IxP IxN 1 V peak VxP VxN 1 V peak Each ADC contains a programmable gain amplifier which allows a gain of 1 2 or 4 The ADC produces full scale output codes with an input of 1 V With a gain of 1 this full scale output corresponds t...

Page 4: ...lters are required to attenuate frequencies above 7 kHz as shown in the Interfacing to Current and Voltage Sensors section MODES OF OPERATION Each ADC has two modes of operation normal mode and disabled mode In the normal mode of operation ADCs are turned on and sample continuously The CHNL_DIS register can be used to disable the ADCs individually There are 2 different power modes available in the...

Page 5: ... buffer from the sinc filter when input is at 1 V peak is 67 107 786 decimal The expected output code in the waveform buffer from the decimator filter when input is at 1 V peak is 74 518 668 See the Waveform Buffer section for more information VOLTAGE REFERENCE The ADE9000 supports a 1 25 V internal reference An external reference can be connected between the REFIN and REFGND pins When using an ex...

Page 6: ...V gmCRITICAL 4 ESRMAX 1000 2 π fCLK Hz 2 C0 CL 2 gmCRITICAL 4 40 1000 2 π 24 576 106 2 7 10 12 8 10 12 2 0 86 The gain of the crystal oscillator circuit in the ADE9000 gm provided in the data sheet is more than 5 times gmCRITICAL therefore there is sufficient margin to start up this crystal Load Capacitor Calculation Crystal manufacturers specify the combined load capacitance across the crystal CL...

Page 7: ...s triggered 26 ms later bringing the IRQ1 pin low and setting the RSTDONE bit in the STATUS1 register The RSTDONE bit being set indicates to the user that the ADE9000 has finished its power up sequence The user can now configure the IC via the serial peripheral interface SPI After configuring the device write the RUN register to start the DSP so that it starts making measurements Note that registe...

Page 8: ...to initiate a software reset the AVDD and DVDD LDOs are turned off The power on sequence resumes from the point where the AVDD and DVDD LDOs are turned on see the Power On Sequence section for details For applications that require putting the ADE9000 into a low power reset state it is recommended to use PSM3 which consumes roughly 2 µA instead of holding the IC in reset with the RESET pin low whic...

Page 9: ...ath To redirect the IA and IC ADC outputs write IA_DIN 010 and IC_DIN 000 in the ADC_REDIRECT register Alternatively the VA voltage channel output can be used for all three datapaths by writing VB_DIN 101 and VC_DIN 101 in the ADC_REDIRECT register The neutral current channel does not offer a zero crossing output or angle measurements To calibrate the phase of the neutral current NI_PCF signal dir...

Page 10: ...be disabled by writing the DISPHPF bit in the CONFIG0 register equal to 1 It is recommended to leave the high pass filter enabled to achieve the metering performance listed in the specifications in the data sheet For some applications it is desirable to increase the high pass filter corner such as to improve performance when a Rogowski coil current sensor is used The high pass filter corner is sel...

Page 11: ...ment of 0 001 This high resolution improves the total active energy and reactive energy performance at low power factors The phase calibration range is 15 to 2 25 at 50 Hz To achieve this calibration range the voltage channel is delayed by one 8 ksps sample 2 25 at 50 Hz 360 DSP LINE f f Delay Channel Voltage 25 2 360 8000 50 Delay Channel Voltage The current channel is then delayed by a digital f...

Page 12: ...e compensation if multipoint phase and gain compensation is enabled the applied current channel phase compensation varies based on the xIRMS input signal level GAIN PHASE CORRECTION MTTHR_L1 MTTHR_H0 MTTHR_H4 FULL SCALE MTTHR_L0 0 REGION0 REGION1 REGION2 REGION3 REGION4 MTTHR_L2 MTTHR_H1 MTTHR_L3 MTTHR_H2 MTTHR_L4 MTTHR_H3 xIGAIN4 xPHCAL4 xIGAIN3 xPHCAL3 xIGAIN2 xPHCAL2 xIGAIN1 xPHCAL1 xIGAIN0 xPH...

Page 13: ...92 10 Cycle RMS 12 Cycle RMS 52 702 092 Resampled Data 18 196 POWER AND FILTER BASED RMS MEASUREMENT ALGORITHMS Filter Based Total RMS The ADE9000 offers current and voltage rms measurements that are calculated by squaring the input signal low pass filtering and then taking the square root of the result The low pass filter LPF2 extracts the rms value attenuating harmonics of a 50 Hz or 60 Hz funda...

Page 14: ... ISUMRMS and ISUMLVL Calculate the desired value of ISUMLVL according to the following equation X SCALE FULL xIRMS ISUMLVL _ _ where xIRMS_Full_Scale is the nominal xIRMS value with full scale inputs 52 702 092 X is the desired current level to indicate a MISMTCH error For example to set ISUMLVL to warn about a vector current sum greater than 10 000 1 from full scale X 10 000 in the previous equat...

Page 15: ...otal reactive power for a 50 Hz signal Table 12 Total Reactive Power Settling Time Total Reactive Power SettlingTime sec Configuration FS 99 FS 99 90 Integrator On HPF On and LPF2 On 0 43 0 59 Integrator Off HPF On and LPF2 On 0 43 0 59 Integrator Off HPF On and LPF2 Off 0 02 0 05 Total Apparent Power Apparent power is generated by multiplying the current rms measurement xIRMS by the corresponding...

Page 16: ...S register value modifies the result in the xFRMS register xxFRMSOS xxFRMS xxFRMS 15 2 0 2 where xxFRMS0 is the initial xFRMS register value before offset calibration Fundamental Active Power The ADE9000 offers fundamental active power measurements using the proprietary fundamental estimation technique The fundamental active power is then gained by xPGAIN and offset correction is applied according...

Page 17: ... line cycles or samples Power factor ITHD and VTHD measurements update every 4096 8 ksps 1 024 sec RMS measurements update every line cycle 10 ms at 50 Hz 10 cycle rms 12 cycle rms measurements update every 10 cycles on a 50 Hz network or 12 cycles on a 60 Hz network The SELFREQ bit in the ACCMODE register defines which network is being used Table 14 Watt Related Register Update Rates Register Nam...

Page 18: ...igned Energy Accumulation Modes Total Active Energy Accumulation Modes In some installations it is desirable to bill for only positive total active energy The ADE9000 offers a way to do this using the WATTACC 1 0 bits in the ACCMODE register To set the total and fundamental active energy accumulation and any corresponding CF pulse output for positive energy only write WATTACC 1 0 to 10 If WATTACC ...

Page 19: ...the same value can be used for all three thresholds X is the desired no load input power level For example to set the no load threshold to zero out energy below 50 000 from full scale X 50 000 in the previous equation Then for a 50 000 1 no load threshold level xNL_LVL is 0x6804 0x6778 488 26 50000 64 066 694 20 _ LVL xNL When a phase is in no load every fDSP 8 ksps zero energy is accumulated into...

Page 20: ...s called half line cycle based accumulation In this mode the zero crossing source to monitor is set by ZX_SEL bits in the ZX_LP_SEL register as shown in Figure 23 Rate ZX TIME EGY Time on Accumulati Energy Internal 1 _ sec With a 50 Hz line frequency the ZX interrupt rate is 100 Hz then the maximum accumulation time is 81 92 sec with EGY_TIME equal to 0x1FFF 8191 decimal sec 92 81 100 1 8191 sec T...

Page 21: ...n use models for energy accumulation Read energy register with reset Accumulate energy over a defined number of line cycles Accumulate energy over a defined number of samples To read energy register with reset use the following settings Configuration register settings EP_CFG register EGY_LD_ACCUM bit 0 EP_CFG register EGY_TMR_MODE bit 0 EP_CFG register RD_RST_EN bit 1 EP_CFG register EGY_PWR_EN bi...

Page 22: ...F frequency output The relationship between the xTHR CFxDEN and AWATT values is given in the following equation CFxDEN xTHR AWATT f CF DTOF 512 Hz Then the maximum recommended CF pulse output frequency is 78 862 kHz kHz 9 78 2 512 0000 _ 0010 x 0 066 694 20 10 096 4 Hz _ 6 CF MAXIMUM where fDTOF is 4 096MHz AWATT is the value at full scale 20 694 066 xTHR is 0x0010_0000 CFDEN is 2 The default CF p...

Page 23: ...cumulation Details Figure 21 shows how AWATT values are accumulated into an internal power accumulator and then are latched into the xWATT_ACC register at a rate of PWRRDY PWRRDY is set after PWR_TIME 1 samples at 8 ksps have been accumulated The power accumulation time can be calculated according to the following equation 8000 1 _ sec TIME PWR Time on Accumulati Power Internal The PWR_TIME 12 0 r...

Page 24: ...crossing circuit is used as the time base for resampling line period angle measurements and energy accumulation using line cycle accumulation mode The xV_PCF and xI_PCF are the voltage and current channel waveforms processed by the DSP and which can be stored into the waveform buffer at a 8 ksps data rate see the Waveform Buffer section for more information The ZX_SRC_SEL bit in the CONFIG0 regist...

Page 25: ...is stable even if one or more phases drops out The input to the zero crossing detection is VA VB VC 2 with the signal chain corresponding to Figure 28 As described in the Applying the ADE9000 to Different Metering Configurations section the ADE9000 can be used to meter different polyphase configurations The VCONSEL 2 0 bits in the ACCMODE register are used to indicate this selection If VCONSEL 2 0...

Page 26: ...n in STATUS1 Register Negative to positive and positive to negative ZXIA ZXIB ZXIC ZXVA ZXVB ZXVC ZXCOMB Not applicable ZXx bit is latched in STATUS1 If cleared it is not set again ZXx interrupt does not occur Zero CrossingTimeout Negative to positive and positive to negative ZXTOVA ZXTOVB ZXTOVC Not applicable Zero crossing timeout is indicated by the ZXTOUT bit in the STATUS1 register and an int...

Page 27: ... Voltage Zero Crossing section and stored in the APERIOD BPERIOD CPERIOD and COM_PERIOD registers respectively The line period calculation is used for the resampling measurement Select which phase voltage line period is used as the basis for resampling calculation using the LP_SEL 1 0 bits in the ZX_LP_SEL register or select a user configured value written in USER_PERIOD using the UPERIOD_SEL bit ...

Page 28: ... is shown in Figure 33 ZXC ZXB PHASE A PHASE B PHASE C A B C PHASE VOLTAGES AFTER LPF1 ZXA NORMAL PHASE SEQUENCE SEQERR 0 15523 033 Figure 33 4 Wire Wye and 4 Wire Delta Normal Phase Sequence For a 4 wire wye or 4 wire delta system VCONSEL 2 0 is 000 010 or 011 as described in the Applying the ADE9000 to Different Metering Configurations section In these 4 wire systems the negative to positive tra...

Page 29: ...ONE registers By default the number of samples used in the calculation varies with measured line frequency The LP_SEL bits in the ZX_LP_SEL register select which line period measurement is used to set the number of samples used in the RMS measurement Alternatively the user can set the number of samples used in the calculation by setting the UPERIOD_SEL bit in CONFIG2 where the user configured USER...

Page 30: ...an the user configured OILVL the overcurrent threshold this is indicated in the OI bit in the STATUS1 register OILVL xIRMSONE 2 5 The OC_EN 3 0 bits in the CONFIG3 register select which phases to monitor for overcurrent events The OIPHASE 3 0 bits in the OISTATUS register indicate which current channels had RMS measurements greater than the threshold If a phase is enabled with the corresponding OC...

Page 31: ...s equation THD on Current Channel A AITHD 2 27 100 A THD calculation is available on the IA IB IC VA VB and VC channels in the AITHD BITHD CITHD AVTHD BVTHD and CVTHD registers respectively Note that a THD measurement is not available on the IN channel TEMPERATURE The ADE9000 includes a temperature measurement unit that uses a temperature sensor in conjunction with a 12 bit successive approximatio...

Page 32: ...n the falling edge of SCLK and the device samples the input data on the rising edge of SCLK Data shifts out of the ADE9000 at the MISO logic output on the falling edge of SCLK and must be sampled by the master device on the rising edge of SCLK The most significant bit of the word is shifted in and out first MISO has an internal weak pull up of 100 kΩ making the default state of the MISO pin high I...

Page 33: ...commended to have the SCLK line idle high An example of what happens when reading the AVGAIN register Address 0x00B when BURST_EN 0 and 1 is shown in Figure 45 SCLK MOSI CMD_HDR 0x00B8 MISO AVGAIN AT 0x00B SS CRC 16 BITS 0 15 0 0 31 0 MISO 0 BURST_EN 0 ADDRESS 0x000 TO ADDRESS 0x6FF BURST_EN 1 ADDRESS 0x000 TO ADDRESS 0x6FF AVGAIN AT 0x00B AVGAIN AT 0x00B 15523 045 Figure 45 SPI Read Protocol Exam...

Page 34: ...NERATOR 0 7 8 15 MISO 16 BIT DATA 15 8 7 0 15523 047 Figure 47 CRC Calculation of 16 Bit SPI Data b0 LFSR FB g0 g1 g2 g15 1 g3 b2 b15 a31 a30 a2 a1 a0 15523 048 Figure 48 LFSR Generator Used for CRC_SPI Calculation Figure 48 shows how the LFSR works The MISO 32 bit data forms the a31 a30 a0 bits used by the LFSR Bit a0 is Bit 24 of the first MISO 32 bit data to enter the LFSR and the last data to ...

Page 35: ...tored in the CRC_RSLT register If any of the monitored registers change value the CRC_RSLT changes as well and the CRC_CHG bit in the STATUS 1 register is set this can also be configured to generate an interrupt on IRQ1 After configuring the ADE9000 and writing the required registers to calibrate the measurements such as xIGAIN or xVGAIN for example the configuration register CRC calculation can b...

Page 36: ... 32 ksps 24 bits shifted left by 4 bits and sign extended to 32 bits Sinc4 IIR LPF Output 2 8 ksps 24 bits shifted left by 4 bits and sign extended to 32 bits Waveforms Processed by the DSP xI_PCF xV_PCF 3 8 ksps 5 27 format The 24 bit sinc4 and sinc4 IIR LPF data is stored as 32 bit in the waveform buffer by shifting by left by 4 bits and sign extending as shown in Table 23 Table 23 24 Bit Sinc4 ...

Page 37: ..._CFG register to start filling the buffer from Address 0x800 When the Address Location 0xFFF in Page 15 is written the filling operation stops To receive an indication when the buffer is full which corresponds to Page 15 being full set Bit 15 of the WFB_PG_IRQEN register prior to starting the capture Then the PAGE_FULL bit in STATUS0 is set when the buffer is full This PAGE_FULL status change can ...

Page 38: ...the LAST_PAGE register can be read instead of using the interrupt 4 Start the capture by writing WF_CAP_EN 1 5 Wait for the buffer to be filled indicated by when the PAGE_FULL interrupt occurs or LAST_PAGE 15 6 When the buffer is filled enable the desired waveform buffer events in the WFB_TRG_CFG register and set the WFB_TRIG_IRQ bit in the STATUS0 to generate an interrupt when the event has occur...

Page 39: ...ne sample per channel seven samples total which are from the same point in time Each resampled waveforms sample is 16 bits wide Figure 51 shows how the resampled waveforms are stored into the buffer Every sample set is separated in memory from the adjacent one by the use of spare cells as shown in Figure 51 These spare cells do not contain any sample data There is one 16 bit spare cell at the end ...

Page 40: ... SPI burst read mode allows samples of data to be read while only sending one SPI command header The transfer of data continues as long as the SS line is kept low and SCLK clocks arrive at the ADE9000 SCLK pin To make it easier to read out the desired data using the SPI burst read functionality the user can indicate which channels of data to read out of the waveform buffer by using the BURST_CHAN ...

Page 41: ... Single Address Read Mode WFB_CAP_SEL 1 and BURST_CHAN 1111 in the WFB_CFG register indicates that there is fixed data rate data in the waveform buffer and the user wants to read out one single address A command is sent to read Address 0x801 which is interpreted as a read to Address 0x801 VA waveform from Address 0x801 is transferred followed by the CRC if BURST_EN 0 If BURST_EN 1 the VA waveform ...

Page 42: ...RST_CHAN 1111 SPI CRC when Reading Waveform Buffer When reading fixed data rate samples with WF_CAP_SEL 1 data read out of the waveform buffer has a CRC calculated which is stored into the CRC_SPI register and can be read back after the waveform buffer burst read When reading a single address of waveform buffer data the CRC_SPI is calculated and appended after the 32 bit data as shown in Figure 54...

Page 43: ...her the ZXVA bit is enabled in MASK1 There are a few interrupts that are nonmaskable meaning that they are generated even if the corresponding bit in the MASKx register is 0 These nonmaskable interrupts include RSTDONE and ERROR0 There is an option to combine all the interrupts onto a single interrupt pin IRQ1 instead of using two pins IRQ0 and IRQ1 To activate this option set the IRQ0_ON_IRQ1 bit...

Page 44: ...ING 90 LAGGING 180 0 IB VBN 15523 056 Figure 56 4 Wire Wye Service Vector Diagram The following figures show common metering configurations 3 wire delta 4 wire delta and 3 wire residential and network The ADE9000 can also measure multiple single phase circuits 180 270 LAGGING 90 LAGGING 0 C B A VBA VAC IA IC IB 15523 057 Figure 57 3 Wire Delta Service Vector Diagram 270 LAGGING 90 LAGGING 180 0 N ...

Page 45: ... are all Blondel compliant ANSI has some meter forms that are not Blondel compliant meaning that there are fewer than n 1 elements so that in a 4 wire wye or 4 wire delta two voltage and three currents are measured The ADE9000 has provisions to deal with non Blondel compliant meter forms Use the VCONSEL 2 0 bits in the ACCMODE register to select what calculation to use for VB based on the VA and V...

Page 46: ...hich can be advantageous if an isolated power supply is used Note that this configuration has poor performance if the phase voltages are not balanced For more information refer to the AN 1334 For this configuration VCONSEL 2 0 000 NEUTRAL VAP VBP VCP VAN AGND DGND VBN VCN VBN VB 220V 120 120 0 353V 220V 120 120 0 353V PHASE C VCN VC PHASE A PHASE B VA 220V 0 220V 120 220V 120 PHASE C PHASE A PHASE...

Page 47: ...neutral terminal of the meter keeping the same circuit as used in Figure 62 or Figure 63 Note that VCONSEL 2 0 must be set to 001 if it is desired to obtain the VAC rms value which is calculated in the BVRMS register and to use the correct phase sequence detection method for the 3 wire delta configuration To calculate the current flowing through IB from the IA and IC measurements set ICONSEL 1 so ...

Page 48: ...uence see the Phase Sequence Error Detection section for more information To obtain the total power active reactive and apparent add the contribution from Phase A Phase B and Phase C APPLYING THE ADE9000 TO A NON BLONDEL COMPLIANT 4 WIRE DELTA SERVICE To use the ADE9000 in a non Blondel compliant 4 wire delta service such as for ANSI meter forms 8S 15S and 24S the Phase A and Phase C voltages are ...

Page 49: ...sensor 1 IB IA IC 3 Wire Delta Isolated Figure 63 with Phase B tied to neutral 2 001 VB VA VC 2 0 IB has current sensor 1 IB IA IC 3 Wire Delta Isolated Figure 66 2 100 VA VA VB VB VA VC VC VC VB 2 0 IB has current sensor 1 IB IA IC 4 Wire Delta Neutral Figure 62 note that VA and VB phasor diagram follows Figure 58 3 000 3 0 4 Wire Wye Non Blondel Compliant Neutral Figure 67 2 010 VB VA VC 3 0 4 W...

Page 50: ...select the energy type to monitor b Configure the TERMSELx bits in the COMPMODE register to select the phases to include in the CF calculation c Program xTHR to 0x00100000 d Compute and program the corresponding CFxDEN register based on the desired impulses per kilowatt hour e Configure the CF pulse width using the CF_LCFG register 10 If energy is monitored using energy registers configure the fol...

Page 51: ... at zero crossings for 1 sec and average them for better accuracy For this example the AIRMS register reading is 5 294 441 The expected AIRMS register reading is IFSP full scale rms codes 0 0947 52 702 092 4 801 488 Therefore the following gain must be applied to reach the expected value 907 0 441 294 5 488 801 4 MEASURED EXPECTED AIRMS AIRMS GAIN The AIGAIN register is calculated as follows AIGAI...

Page 52: ...ionFSP VFSP Full Scale Power Codes Accumulation Time 8000 2 13 0 0002 0 311 20 694 066 10 sec 8000 2 13 12570 0xA1 161 2 8000 10 000 11 12570 13 AWATTOS 5 To compute AVAROS apply a nominal voltage and offset calibration current at power factor 0 Follow similar steps to obtain BPGAIN BWATTOS BVAROS CPGAIN CWATTOS and CVAROS CONVERSION CONSTANTS Conversion constants are used to convert ADE9000 regis...

Page 53: ...L1 Phase A multipoint phase correction factor If multipoint phase and gain calibration is disabled with MTEN 0 in the CONFIG0 register the APHCAL0 phase compensation is applied If multipoint phase and gain correction is enabled with MTEN 1 the APHCAL0 through APHCAL4 value is applied based on the AIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values 0x00000000 R W 0x008 APHCAL2...

Page 54: ...nd the MTTHR_Lx and MTTHR_Hx register values 0x00000000 R W 0x026 BPHCAL0 Phase B multipoint phase correction factor If multipoint phase and gain calibration is disabled with MTEN 0 in the CONFIG0 register the BPHCAL0 phase compensation is applied If multipoint phase and gain correction is enabled with MTEN 1 the BPHCAL0 through BPHCAL4 value is applied based on the BIRMS current rms amplitude and...

Page 55: ... 0x00000000 R W 0x045 CIGAIN4 Phase C Multipoint gain correction factor If multipoint gain and phase compensation is enabled with MTEN 1 in the CONFIG0 register an additional gain factor CIGAIN0 through CIGAIN5 is applied based on the CIRMS current rms amplitude and the MTTHR_Lx and MTTHR_Hx register values 0x00000000 R W 0x046 CPHCAL0 Phase C multipoint phase correction factor If multipoint phase...

Page 56: ...See MTTHR_L0 for more information 0x00000000 R W 0x069 MTTHR_H3 Multipoint phase gain threshold See MTTHR_L0 for more information 0x00000000 R W 0x06A MTTHR_H4 Multipoint phase gain threshold See MTTHR_L0 for more information 0x00000000 R W 0x06B NIRMSOS Neutral current rms offset for the NIRMS calculation 0x00000000 R W 0x06C ISUMRMSOS Offset correction for the ISUMRMS calculation based on the su...

Page 57: ...BVTHD Phase B voltage THD updated every 1 024 sec 0x00000000 R 0x238 BITHD Phase B current THD updated every 1 024 sec 0x00000000 R 0x239 BIRMSONE Phase B current fast RMS calculation one cycle rms updated every half cycle 0x00000000 R 0x23A BVRMSONE Phase B voltage fast RMS calculation one cycle rms updated every half cycle 0x00000000 R 0x23B BIRMS1012 Phase B current fast 10 cycle rms 12 cycle r...

Page 58: ...ve power updated after PWR_TIME 8 kSPS samples 0x00000000 R 0x2F0 AVARHR_LO Phase A accumulated total reactive energy LSB Updated according to the settings in the EP_CFG and EGY_TIME registers 0x00000000 R 0x2F1 AVARHR_HI Phase A accumulated total reactive energy MSB Updated according to the settings in the EP_CFG and EGY_TIME registers 0x00000000 R 0x2F9 AVA_ACC Phase A accumulated total apparent...

Page 59: ...000 R 0x354 BFVAHR_LO Phase B accumulated fundamental apparent energy LSB Updated according to the settings in the EP_CFG and EGY_TIME registers 0x00000000 R 0x355 BFVAHR_HI Phase B accumulated fundamental apparent energy MSB Updated according to the settings in the EP_CFG and EGY_TIME registers 0x00000000 R 0x35D CWATT_ACC Phase C accumulated total active power updated after PWR_TIME 8 kSPS sampl...

Page 60: ...t in the CONFIG3 register and AIRMSONE greater than the OILVL threshold this value is updated 0x00000000 R 0x40B OIB Phase B overcurrent RMS value If a phase is enabled with the OC_ENB bit set in the CONFIG3 register and BIRMSONE greater than the OILVL threshold this value is updated 0x00000000 R 0x40C OIC Phase C overcurrent RMS value If a phase is enabled with the OC_ENC bit set in the CONFIG3 r...

Page 61: ...ings on Phase A and Phase C voltages 0x0000 R 0x485 ANGL_VA_IA Time between positive to negative zero crossings on Phase A voltage and current 0x0000 R 0x486 ANGL_VB_IB Time between positive to negative zero crossings on Phase B voltage and current 0x0000 R 0x487 ANGL_VC_IC Time between positive to negative zero crossings on Phase C voltage and current 0x0000 R 0x488 ANGL_IA_IB Time between positi...

Page 62: ... sinc4 output at 32 kSPS 0x00000000 R 0x506 NI_SINC_DAT Neutral current channel ADC waveforms from the sinc4 output at 32 kSPS 0x00000000 R 0x510 AI_LPF_DAT Current channel A ADC waveforms from the sinc4 IIR LPF output at 8 kSPS 0x00000000 R 0x511 AV_LPF_DAT Voltage channel A ADC waveforms from the sinc4 IIR LPF output at 8 kSPS 0x00000000 R 0x512 BI_LPF_DAT Current channel B ADC waveforms from th...

Page 63: ...nized functionally See BFVA 0x00000000 R W 0x628 CFVA_1 SPI burst read accessible Registers organized functionally See CFVA 0x00000000 R W 0x629 AFIRMS_1 SPI burst read accessible Registers organized functionally See AFIRMS 0x00000000 R W 0x62A BFIRMS_1 SPI burst read accessible Registers organized functionally See BFIRMS 0x00000000 R W 0x62B CFIRMS_1 SPI burst read accessible Registers organized ...

Page 64: ...BITHD_2 SPI burst read accessible Registers organized by phase See BITHD 0x00000000 R W 0x69E BFWATT_2 SPI burst read accessible Registers organized by phase See BFWATT 0x00000000 R W 0x69F BFVA_2 SPI burst read accessible Registers organized by phase See BFVA 0x00000000 R W 0x6A0 BFIRMS_2 SPI burst read accessible Registers organized by phase See BFIRMS 0x00000000 R W 0x6A1 BFVRMS_2 SPI burst rea...

Page 65: ... VNOM in the computation of Phase C total apparent power CVA 0x0 R W 9 VNOMB_EN Set this bit to use the nominal phase voltage rms VNOM in the computation of Phase B total apparent power BVA 0x0 R W 8 VNOMA_EN Set this bit to use the nominal phase voltage rms VNOM in the computation of Phase A total apparent power AVA 0x0 R W 7 RMS_SRC_SEL This bit selects which samples are used for the RMS and 10 ...

Page 66: ...APHCAL0 0001 AIGAIN1 APHCAL1 0010 AIGAIN2 APHCAL2 0011 AIGAIN3 APHCAL3 0100 AIGAIN4 APHCAL4 1111 This feature is disabled because MTEN 0 in the CONFIG0 register 0x23D BMTREGION 31 4 RESERVED Reserved 0x0 R 3 0 BREGION If multipoint gain and phase compensation is enabled with MTEN 1 in the CONFIG0 register these bits indicate which BIGAINx and BPHCALx is currently being used 0xF R 0000 BIGAIN0 BPHC...

Page 67: ... a new temperature measurement is available 0x0 R W1 24 MISMTCH This bit is set to indicate a change in the relationship between ISUMRMS and ISUMLVL 0x0 R W1 23 COH_WFB_FULL This bit is set when the waveform buffer is full with resampled data which is selected when WF_CAP_SEL 0 in the WFB_CFG register 0x0 R W1 22 WFB_TRIG This bit is set when one of the events configured in WFB_TRIG_CFG occurs 0x0...

Page 68: ... R W1 5 REVRPB This bit indicates if the Phase B total or fundamental reactive power has changed sign See REVRPC 0x0 R W1 4 REVRPA This bit indicates if the Phase A total or fundamental reactive power has changed sign See REVRPC 0x0 R W1 3 REVAPC This bit indicates if the Phase C total or fundamental active power has changed sign The PWR_SIGN_SEL bit in the EP_CFG register selects whether total or...

Page 69: ...t to indicate that the IC finished its power up sequence after a reset or after changing between PSM3 operating mode to PSM0 which indicates that the user can configure the IC via the SPI port 0x0 R W1 15 ZXIC When this bit is set to 1 it indicates a zero crossing is detected on Phase C current 0x0 R W1 14 ZXIB When this bit is set to 1 it indicates a zero crossing is detected on Phase B current 0...

Page 70: ... phases are out of no load This bit goes to zero when one or more phases of total apparent energy accumulation goes into no load 0x0 R 14 RFNOLOAD This bit is set when the fundamental reactive energy accumulations in all phases are out of no load This bit goes to zero when one or more phases of fundamental reactive energy accumulation goes into no load 0x0 R 13 AFNOLOAD This bit is set when the fu...

Page 71: ...ondition 0x0 R 2 DIPC This bit is equal to one when the Phase C voltage is in the dip condition and is zero when it is not in a dip condition 0x0 R 1 DIPB This bit is equal to one when the Phase B voltage is in the dip condition and is zero when it is not in a dip condition 0x0 R 0 DIPA This bit is equal to one when the Phase A voltage is in the dip condition and is zero when it is not in a dip co...

Page 72: ...it to enable an interrupt when the CF4 polarity changed sign 0x0 R W 9 REVPSUM3 Set this bit to enable an interrupt when the CF3 polarity changed sign 0x0 R W 8 REVPSUM2 Set this bit to enable an interrupt when the CF2 polarity changed sign 0x0 R W 7 REVPSUM1 Set this bit to enable an interrupt when the CF1 polarity changed sign 0x0 R W 6 REVRPC Set this bit to enable an interrupt when the Phase C...

Page 73: ...ELLC Set this bit to enable an interrupt when the Phase C voltage enters a swell condition 0x0 R W 21 SWELLB Set this bit to enable an interrupt when the Phase B voltage enters a swell condition 0x0 R W 20 SWELLA Set this bit to enable an interrupt when the Phase A voltage enters a swell condition 0x0 R W 19 RESERVED Reserved 0x0 R 18 SEQERR Set this bit to enable an interrupt when on a phase sequ...

Page 74: ...no load condition 0x0 R W 0 ANLOAD Set this bit to enable an interrupt when one or more phase total active energy enters or exits the no load condition 0x0 R W 0x407 EVENT_MASK 31 17 RESERVED Reserved 0x0 R 16 DREADY Set this bit to enable the EVENT pin to go low when new waveform samples are ready The update rate depends on the data selected in the WF_SRC bits in the WFB_CFG register 0x0 R W 15 V...

Page 75: ...N Set this bit to enable the EVENT pin to go low to indicate that the Phase B voltage is in a dip condition 0x0 R W 0 DIPAEN Set this bit to enable the EVENT pin to go low to indicate that the Phase A voltage is in a dip condition 0x0 R W 0x409 OILVL 31 24 RESERVED Reserved 0x0 R 23 0 OILVL_VAL Over current detection threshold level 0xFFFFFF R W 0x40A OIA 31 24 RESERVED Reserved 0x0 R 23 0 OI_VAL ...

Page 76: ...CFVANL This bit is set if the Phase C fundamental apparent energy is in no load 0x0 R 16 CFVARNL This bit is set if the Phase C fundamental reactive energy is in no load 0x0 R 15 CFWATTNL This bit is set if the Phase C fundamental active energy is in no load 0x0 R 14 CVANL This bit is set if the Phase C total apparent energy is in no load 0x0 R 13 CVARNL This bit is set if the Phase B total reacti...

Page 77: ...s for 000b through 110b match VC_DIN When the value is equal to 111b then 0x7 R W 111 VB ADC data 14 12 VA_DIN VA channel data can be selected from all channels The bit descriptions for 000b through 110b match VC_DIN When the value is equal to 111b then 0x7 R W 111 VA ADC data 11 9 IN_DIN IN channel data can be selected from all channels The bit descriptions for 000b through 110b match VC_DIN When...

Page 78: ...x474 TEMP_TRIM 31 16 TEMP_OFFSET Offset of temperature sensor calculated during the manufacturing process 0x0 R W 15 0 TEMP_GAIN Gain of temperature sensor calculated during the manufacturing process 0x0 R W 0x481 CONFIG1 15 EXT_REF Set this bit if using an external voltage reference 0x0 R W 14 13 RESERVED Reserved 0x0 R 12 IRQ0_ON_IRQ1 Set this bit to combine all the interrupts onto a single inte...

Page 79: ...s accumulated in the digital to frequency converter 0x0 R W 14 CF3DIS CF3 output disable See CF4DIS 0x0 R W 13 CF2DIS CF2 output disable See CF4DIS 0x0 R W 12 CF1DIS CF1 output disable See CF4DIS 0x0 R W 11 9 CF4SEL Type of energy output on the CF4 pin Configure TERMSEL4 in the COMPMODE register to select which phases are included 0x0 R W 000 Total active power 001 Total reactive power 010 Total a...

Page 80: ...ters and CFx pulses 0x0 R W 00 Signed accumulation mode 01 Absolute value accumulation mode 10 Positive accumulation mode 11 Negative accumulation mode 1 0 WATTACC Total and fundamental active power accumulation mode for energy registers and CFx pulses See VARACC 0x0 R W 0x493 CONFIG3 15 12 OC_EN Overcurrent detection enable OC_EN 3 0 bits can all be set to 1 simultaneously to allow overcurrent de...

Page 81: ...F3 datapath The CF3 energy is positive if this bit is clear and negative if this bit is set 0x0 R 7 SUM2SIGN Sign of the sum of the powers included in the CF2 datapath The CF2 energy is positive if this bit is clear and negative if this bit is set 0x0 R 6 SUM1SIGN Sign of the sum of the powers included in the CF1 datapath The CF1 energy is positive if this bit is clear and negative if this bit is ...

Page 82: ... Stop when waveform buffer is full 01 Continuous fill stop only on enabled trigger events 10 Continuous filling center capture around enabled trigger events 11 Continuous fill save event address of enabled trigger events 5 WF_CAP_SEL This bit selects whether the waveform buffer is filled with resampled data or fixed data rate data selected in the WF_CAP_SEL bits 0x0 R W 0 Resampled data 1 Fixed da...

Page 83: ...e put into the waveform buffer after a trigger event occurred which is within a sample or two of when the actual trigger event occurred 0x0 R 0x4AF CONFIG2 15 13 RESERVED Reserved 0x0 R 12 UPERIOD_SEL Set this bit to use a user configured line period in USER_PERIOD for the VRMS 10 cycle rms 12 cycle rms and resampling calculation If this bit is clear the phase voltage line period selected by the L...

Page 84: ... set in the STATUS1 register 0x0 R W 0x4B5 CRC_OPTEN 15 CRC_WFB_TRG_CFG_EN Set this bit to include the WFB_TRG_CFG register in the configuration register CRC calculation 0x0 R W 14 CRC_WFB_PG_IRQEN Set this bit to include the WFB_PG_IRQEN register in the configuration register CRC calculation 0x0 R W 13 CRC_WFB_CFG_EN Set this bit to include the WFB_CFG register in the configuration register CRC c...

Page 85: ...sec 0x4B7 TEMP_RSLT 15 12 RESERVED Reserved 0x0 R 11 0 TEMP_RESULT 12 bit temperature sensor result 0x0 R 0x4B9 PGA_GAIN 15 14 RESERVED Reserved 0x0 R 13 12 VC_GAIN PGA gain for voltage Channel C ADC 0x0 R W 00 Gain 1 01 Gain 2 10 Gain 4 11 Gain 4 11 10 VB_GAIN PGA gain forVoltage Channel B ADC SeeVC_GAIN 0x0 R W 9 8 VA_GAIN PGA gain forVoltage Channel A ADC SeeVC_GAIN 0x0 R W 7 6 IN_GAIN PGA gain...

Page 86: ...s for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Information contained within this document is subject to change without notice Software or hardware prov...

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