UG-1098
ADE9000 Technical Reference Manual
Rev. 0 | Page 50 of 86
QUICK START
This section describes how to set up the
for a 3-phase,
4-wire wye measurement. Figure 62 shows the typical hardware
connection for a 3-phase, 4-wire wye configuration.
1.
Wait for the RSTDONE interrupt, indicated by the IRQ pin
going low.
2.
Configure PSM0 normal power mode by setting the
PM1 pin and the PM0 pin to low.
3.
Configure PGA gain on current and voltage channels using
the PGA_GAIN gain register. The default gain on all
channels is 1.
4.
Configure the HPFDIS bits in the CONFIG0 register to
enable/disable the high-pass filter. The high-pass filter is
enabled by default. It is recommended to keep the high-
pass filter enabled. Set the desired corner frequency for
HPF using the HPF_CRN bits in the CONFIG2 register.
The default value for HPF_CRN is 6 (1.25 Hz).
5.
If Rogowski coils are used as current sensors, enable the
digital integrator using the INTEN and INITEN bits in the
CONFIG0 register. Disable the integrator when using
current transformers. The digital integrators are disabled
by default.
a.
If an integrator is enabled, set the DICOEFF register
to 0xFFFFE000.
6.
Configure the expected fundamental frequency using the
SELFREQ bit (50 Hz: SELFREQ = 0, 60 Hz: SELFREQ = 1)
in the ACCMODE register, and program the nominal voltage
in the VLEVEL register for fundamental calculations.
VLEVEL = X × 1,144,084, where X is the dynamic range
that the nominal signal is at with respect to full scale.
7.
Configure the zero-crossing source for ZX detection. If
ZX_SRC_SEL = 1 in the CONFIG0 register, data before the
HPF, integrator, and phase compensation is used. If
ZX_SRC_SEL = 0, data after the HPF, integrator, and phase
compensation is used. It is recommended to have
ZX_SRC_SEL = 0.
8.
Set VCONSEL = 000 in the ACCMODE register for a
3-phase, 4-wire wye configuration.
9.
If energy is monitored using the CF outputs, configure the
following registers. Skip this section if the CF outputs are
not used.
a.
Configure the CFxSEL bits in the CFMODE register
to select the energy type to monitor.
b.
Configure the TERMSELx bits in the COMPMODE
register to select the phases to include in the CF
calculation.
c.
Program xTHR to 0x00100000.
d.
Compute and program the corresponding CFxDEN
register based on the desired impulses per kilowatt-hour.
e.
Configure the CF pulse width using the CF_LCFG
register.
10.
If energy is monitored using energy registers, configure the
following registers:
a.
Configure the WATTACC and VARACC bits in the
ACCMODE register to select amongst available
accumulation modes (for example: signed, absolute,
positive, or negative accumulation mode). The default
accumulation mode is signed.
b.
Configure the NOLOAD_TMR bits in the EP_CFG
register and set the ACT_NL_LVL, REACT_NL_LVL,
and APP_NL_LVL level registers to detect no load and
prevent energy accumulation of noise.
c.
Configure the EGY_TMR_MODE bit in the EP_CFG
register to select sample (EGY_TMR_MODE = 0) or
line cycle (EGY_TMR_MODE = 1) accumulation. Set
the desired samples or half line cycles in the
EGY_TIME register.
d.
Configure the EGY_LD_ACCUM bit in the EP_CFG
register to add the internal energy register to user energy
register on EGYRDY (EGY_LD_ACCUM = 0), or to
overwrite the user energy register with the internal
energy register value (EGY_LD_ACCUM = 1).
e.
Configure the RD_RST_EN bit in the EP_CFG
register to enable reset of user energy registers on read
(RD_RST_EN = 1), or to disable reset of user energy
registers on read (RD_RST_EN = 0).
11.
can provide interrupts for a variety of events
on the IRQ0 and IRQ1 pins. The MASK0 or MASK1 and
STATUS0 or STATUS1 registers manage the respective
interrupt pins.
12.
See the Power Quality Measurements section to configure
the power quality parameters.
13.
See the Waveform Buffer section to configure and use the
waveform buffer.
14.
Enable the DSP by setting the RUN register = 1, and enable
energy accumulation by setting the EGY_PWR_EN bit in
the EP_CFG register = 1.
15.
Note that calibration is performed once at typical operating
conditions. When the calibration values are computed,
write the constants to registers before enabling the DSP.
16.
enable write protection by writing 0x3C64 to the
WR_LOCK register.
