ADE9000 Technical Reference Manual
UG-1098
Rev. 0 | Page 33 of 86
SPI WRITE
A write operation using the SPI interface of the
initiated when the SS pin goes low and the
receives a
16-bit command header (CMD_HDR) with CMD_HDR[3]
equal to 0.
The 16-bit or 32-bit data to be written follows the command
header, with the most significant bit first.
After the last bit of data has been clocked out, the master must
bring the SS line high to release the SPI bus. It is recommended
to have the SCLK line idle high.
SPI READ
A read operation using the SPI interface of the
initiated when the SS pin goes low and the
receives a
16-bit command header (CMD_HDR) with CMD_HDR[3]
equal to 1.
The 16-bit or 32-bit data from the register follows the command
header, with the most significant bit first.
The CRC of the register data is appended if
•
BURST_EN = 0 and the address is within the range of
0x000 to 0x6FF.
•
BURST_EN = 0 and the address is in the waveform buffer,
0x800 to 0xFFF, and BURST_CHAN is equal to 1111 (binary).
The
provides a SPI burst read functionality: instead
of sending the CRC, the following data is from the next address
if the following conditions apply (see the SPI Burst Read section
for more information):
•
BURST_EN = 1, and the address is within the range of
0x500 to 0x63C or 0x680 to 0x6BC.
•
The address is within the range of 0x800 to 0xFFF, and
BURST_CHAN is not equal to 1111 (binary).
If none of these cases apply, and extra clocks are sent, the
original read data is resent.
Table 20 summarizes which data is sent after the data from the
register addressed in the CMD_HDR; it varies based on the
address being accessed and the BURST_EN selection.
Table 20. Data Clocked Out After Addressed Data, in SPI
Read Operation
Address
BURST_EN = 0
BURST_EN = 1
0x000 to 0x4FF
CRC
Same data is resent
0x500 to 0x6FF
CRC
Next address
0x800 to 0xFFF
(Waveform Buffer)
If BURST_CHAN =
1111, CRC;
otherwise, next
address
If BURST_CHAN =
1111, same data is
resent; otherwise, next
address
The SS line can be brought high before clocking out the CRC if
this information is not needed in the application.
After the last bit of data, or CRC, has been clocked out, the
master must bring the SS line high to release the SPI bus. Then
the
stops driving MISO and enables a 100 kΩ weak
pull-up. It is recommended to have the SCLK line idle high.
An example of what happens when reading the AVGAIN register,
Address 0x00B, when BURST_EN = 0 and 1 is shown in Figure 45.
SCLK
MOSI
CMD_HDR = 0x00B8
MISO
AVGAIN AT 0x00B
SS
CRC, 16 BITS
0 15
0
0
31
0
MISO
0
BURST_EN = 0
ADDRESS 0x000 TO
ADDRESS 0x6FF
BURST_EN = 1,
ADDRESS 0x000 TO
ADDRESS 0x6FF
AVGAIN AT 0x00B
AVGAIN AT 0x00B
15523-
045
Figure 45. SPI Read Protocol Example where the Following Data is the CRC
or the Initial Data is Repeated
SPI BURST READ
SPI burst read allows multiple registers to be read after sending
one CMD_HDR. After the register data has been clocked out,
the
auto-increments the address and starts clocking
out the data from the next register address.
SPI burst read access is available on registers with addresses
ranging from 0x500 0x6FF and in the waveform buffer, with
Address 0x800 to Address 0xFFF. SPI burst read is not available
on other register addresses. A SPI burst read operation occurs
for the options in Table 20 where next address is shown.
To enable burst read functionality on the registers from 0x500
to 0x6FF, set the BURST_EN bit in the CONFIG1 register to 1.
The waveform buffer burst read functionality is enabled by
default and is managed by the BURST_CHAN[3:0] bits of the
WFB_CFG register. If these bits are set to 1111 (binary), the
burst read functionality of the waveform buffer is disabled. For
further details on burst read operation of waveform buffer
contents, see the Burst Read Waveform Buffer Samples from SPI
section.
A burst read operation using the SPI interface of the
is initiated when the SS pin goes low and the
receives a
16-bit command header (CMD_HDR) with CMD_HDR[3]
equal to 1, which meets the criteria in Table 20 where next
address is shown.
Following the command header,
data for the register addressed in the command. After the last
bit of the first register value is received, the
auto-
increments the address and starts clocking out the data from the
next register address. If the starting address is in the range of
Address 0x500 to Address 0x516 and the SPI is clocked beyond
Address 0x516, the address is auto-incremented until it reaches
Address 0x5FF and then wraps back to the initial address. If the
initial address is in the Address 0x600 to Address 0x63C or
Address 0x680 to Address 0x6BC range and the SPI is clocked
beyond Address 0x63C or Address 0x6BC, the address wraps
back to the initial address. This process continues until the
