ADE9000 Technical Reference Manual
UG-1098
Rev. 0 | Page 29 of 86
ZXA_POS ZXC_NEG
PHASE A
= VAB
PHASE C
= VCB
VA,VC
AFTER LPF1
ZXC_POS
NORMAL PHASE SEQUENCE
SEQERR = 0
ZXA_NEG
15523-
036
Figure 36. 3-Wire Delta Normal Phase Sequence
Write SEQ_CYC to indicate how many consecutive incorrect
transitions must be observed before raising the SEQ_ERR
interrupt. It is recommended to set SEQ_CYC to 1. Figure 37
shows an installation error for 3-wire delta that results in a
detected phase sequence error.
15523-
037
ZXC_POS
PHASE A
PHASE C
VA, VB, VC
AFTER LPF1
STATUS1.
SEQERR
ZXC_NEG
STATUS1.SEQERR
SET TO 1
WRITE STATUS1.SEQERR = 1
TO ACKNOWLEDGE THIS EVENT
AND CLEAR STATUS1.SEQERR
ZXA_POS
ZXA_NEG
Figure 37. 3-wire Delta Phase Sequence Error (Wiring Error)
Figure 38 shows that in an installation with the normal phase
sequence, a phase sequence error is generated if one of the
phase voltage drops below the ZXTHRSH.
PHASE A
PHASE C
VA,VB,VC
AFTERLPF1
STATUS1.
SEQERR
ZXC_NEG
ZXA_POS
ZXA_NEG
ZXA_NEG
ZXA_POS
ZXA_POS
ZXA_NEG
STATUS1.SEQERR
SETTO1
WRITE STATUS1.SEQERR = 1
TO ACKNOWLEDGE THIS EVENT
AND CLEAR STATUS1.SEQERR
ZXC_POS
15523-
038
Figure 38. 3-Wire Delta Phase Sequence Error from a Phase Voltage
Dropping Below ZXTHRSH with SEQ_CYC = 1
Fast RMS½ and 10/12 RMS Measurements
RMS½ is an rms measurement done over one line cycle,
updated every half cycle.
This measurement is provided for voltage and current on all
phases plus the neutral current. All the half cycle rms
measurements are done over the same time interval and update
at the same time, as indicated by the RMSONERDY bit in the
STATUS0 register. The results are stored in the AIRMSONE,
BIRMSONE, CIRMSONE, NIRMSONE, AVRMSONE,
BVRMSONE, and CVRMSONE registers.
By default, the number of samples used in the calculation varies
with measured line frequency. The LP_SEL bits in the ZX_LP_SEL
register select which line period measurement is used to set the
number of samples used in the RMS½ measurement.
Alternatively, the user can set the number of samples used in
the calculation by setting the UPERIOD_SEL bit in CONFIG2,
where the user configured USER_PERIOD register is used
instead of the selected line period measurement. For more
information about USER_PERIOD and the line period
measurements, see the Line Period Calculation section.
The samples used for the RMS½ calculation can come from
before the high-pass filter or after the integrator, as selected in
the RMS_SRC_SEL bit in the CONFIG0 register.
Because the high-pass filter has a significant settling time
associated with it, it is recommended to use the data from
before the high-pass filter for the fastest response time.
An offset correction register is provided for even better
performance with small input signal levels, xRMSONEOS.
The xRMSONE register reading with full-scale inputs is
52,702,092 (decimal).
The 10 cycle rms/12 cycle rms measurement is done over 10 cycles
on a 50 Hz network, or 12 cycles on a 60 Hz network.
An offset correction register is provided for even better
performance with small input signal levels, xRMS1012OS.
The xRMS1012 register reading with full scale inputs is
52,702,092 (decimal).
Table 18 shows the ½ cycle rms settling times for a 50 Hz signal.
Table 19 shows the 10 cycle rms/12 cycle rms settling times for a
50 Hz signal.
Table 18. ½ RMS Settling Time
Configuration
½ RMS Settling Time,
FS = 99% (sec)
Integrator On, HPF On, and LPF2 On
0.26
Integrator Off, HPF On, and LPF2 On
0.06
Table 19. 10 Cycle RMS/12 Cycle RMS Settling Time
Configuration
10/12 RMS Settling Time,
FS = 99% (sec)
Integrator On, HPF On, and LPF2 On
0.6
Integrator Off, HPF On, and LPF2 On
0.2
