UG-1098
ADE9000 Technical Reference Manual
Rev. 0 | Page 20 of 86
Energy Accumulation Details
Internal Energy Register Overflow Rate
There are 42-bit internal signed energy accumulators for each
phase of each energy accumulation, as shown in Figure 21. These
accumulators update at a rate of f
DSP
= 8 ksps. The following
equation shows how to calculate the time until the internal
accumulator overflows with full-scale inputs and all digital gain
and offset factors at zero, where AWATT_AT_FULL_SCALE
refers to the nominal AWATT value with full scale inputs.
×
=
DSP
f
SCALE
FULL
AT
AWATT
Time
r
Accumulato
Energy
Internal
Maximum
_
_
_
2
(sec)
41
For example, with CONFIG0.MTEN equal to zero, for single-
point gain compensation and AIGAIN, AVGAIN, APGAIN,
and AWATTOS all equal to zero, the Phase A total active energy
has a digital gain of 1. Then, the Phase A total active energy
accumulated in the internal accumulator overflows in 13.3 sec
with the nominal full-scale AWATT value of 20,694,066.
sec
3
.
13
8000
20,694,066
2
(sec)
41
=
×
=
Time
r
Accumulato
Energy
Internal
Maximum
User Energy Register Update Rate, EGYRDY
As shown in Figure 21, the internal energy accumulator is
latched into a user accessible energy register or added to user
accessible register at a rate of EGYRDY. Figure 23 further
describes how the EGYRDY update rate is generated.
The EGYRDY update rate occurs after EG 1 f
DSP
samples or EG 1 half line cycles, according to the
EGY_TMR_MODE bit in the EP_CFG register.
If EGY_TMR_MODE is zero, the internal energy register
accumulates for EG 1 samples at 8 ksps. This mode
is called sample-based accumulation.
+
=
DSP
f
TIME
EGY
Time
on
Accumulati
Energy
Internal
1
_
(sec)
The EGY_TIME[12:0] register allows up to (8191 + 1) =
8192 samples to be accumulated, which corresponds to
8192/8000 = 1.024 sec if EGY_TMR_MODE is equal to zero.
sec
024
.
1
8000
1
8191
(sec)
=
+
=
Time
on
Accumulati
Energy
Internal
If EGY_TMR_MODE is 1, the internal energy register
accumulates for EG 1 half line cycles at 8 ksps. This
mode is called half line cycle-based accumulation. In this mode,
the zero-crossing source to monitor is set by ZX_SEL bits in the
ZX_LP_SEL register, as shown in Figure 23.
+
=
Rate
ZX
TIME
EGY
Time
on
Accumulati
Energy
Internal
1
_
(sec)
With a 50 Hz line frequency, the ZX interrupt rate is 100 Hz,
then the maximum accumulation time is 81.92 sec with
EGY_TIME equal to 0x1FFF, 8191 (decimal):
sec
92
.
81
100
1
8191
(sec)
=
+
=
Time
on
Accumulati
Energy
Internal
Note that the internal energy register overflows in 13.3 sec with
full-scale inputs; therefore, EGY_TIME must be set lower than
1329 (decimal) to prevent overflow when EGY_TMR_MODE is 1.
ENERGY
POWER
0
ZX_LP_SEL.
ZX_SEL
1
11
10
ZXVA
ZXVB
ZXVC
ZXCOMB
00
01
CONFIG1.
CF3_CFG
CF3
0
1
EP_CFG.EGY_TMR_MODE
CF3/ZXPIN
COUNTER
EGY_TIME[12:0] + 1
EGYRDY UPDATERATE
STATUS0.EGYRDY
COUNTER
PWR_TIME[12:0] + 1
EQUAL?
EQUAL?
PWRRDY UPDATE RATE
STATUS0.PWRRDY
f
DSP
f
DSP
15523-
023
Figure 23. EGYRDY and PWRRDY Update Rate
Reloading or Accumulating User Energy Register
When the EGYRDY event happens, the internal energy
accumulation is either directly loaded into the xWATTHR register
or added to the existing accumulation based on the state of the
EGY_LD_ACCUM bit in the EP_CFG register. The internal
energy register is reset and starts counting again from zero.
If EGY_LD_ACCUM is equal to zero, the internal energy register is
added to the user accessible energy register. If EGY_LD_ACCUM
is equal to one, the internal energy register overwrites the user
accessible energy register.
User Energy Register Overflow Rate
The energy registers in the
are signed and 45 bits
wide, split between two 32-bit registers, as shown in Figure 24.
These accumulators update at a rate according to EGYRDY, as
described in the User Energy Register Update Rate, EGYRDY
section. The following equation shows how to calculate the time
until the user accessible accumulator overflows with full-scale
inputs and all digital gain and offset factors at zero, where
AWATT_AT_FULL_SCALE refers to the nominal AWATT
value with full-scale inputs. For this example, assume that the
internal energy register is updating at every f
DSP
= 8 ksps sample.
×
=
DSP
f
SCALE
FULL
AT
AWATT
Time
r
Accumulato
Energy
Internal
Maximum
_
_
_
2
(sec)
44
