AS7030B/AS7038GB/AS7038RB
Software Description
Eval Kit Manual
• PUBLIC
UG001014
• v1-00 • 2021-May-06
53
│ 37
subsampling will be enabled
1
. Please refer to Sampling Rate and Subsampling for details on sampling
rate.
Use this window to enable/disable ADC channels.
Any change in the values of the fields for sample frequency, sample period, cycle period and in the
ADC channel selection will cause a new calculation of the values for the rest of the fields.
For further information, please refer to the following document:
●
AS7030B/AS7038GB/AS7038RB Datasheet.
ADC Configuration
This window configures the clock divider of the 1 MHz ADC input clock and the ADC settling periods.
ADC channels are enabled in the Sequencer Configuration window. The selection is shown below.
Figure 36:
ADC Configuration Submenu
Figure 37:
ADC Block Diagram
For further information, please refer to the following documents:
●
AS7030B/AS7038GB/AS7038RB Datasheet
1
For example, with one ADC channel enabled and desired sample rate of 200 Hz, the sequencer cycle period needs to be
5000 µs. If (1) is 10, the SEQ_PER register should be 500, but as it is 8 bits, it cannot fit the value 500. It is also not
advisable to increase the clock divider as that will affect all the other timing settings, it is better to keep that small to give finer
granularity of the timing. To achieve the 200 Hz sample rate, the cycle period will be set to 250 and subsampling enabled with
subsampling ratio of 2
– meaning the ADC will be triggered every 2
nd
sequencer cycle. That will give a sample rate of 200 Hz /
5000 µs period.
