AS7030B/AS7038GB/AS7038RB
AS7030B/AS7038GB/AS7038RB Overview
Eval Kit Manual
• PUBLIC
UG001014
• v1-00 • 2021-May-06
53
│ 22
The register SEQ_CFG and SD_SUBS configure how subsampling will be executed:
●
sd_subs field in SD_SUBS register defines if subsampling is enabled; when it is 0, no
subsampling is done
– every sequencer cycle triggers an ADC measurement (Figure 18);
setting to N>0, enables subsampling and then for N sequencer cycles the sequencer will not
trigger the ADC, followed by one cycle with ADC conversion.
●
sd_subs_always bit in SEQ_CFG register defines if all enabled ADC channels are subject to
subsampling. Using this only makes sense for more than one enabled ADC channel.
●
sd_subs_always = 1: subsampling of all enabled ADC channels (Figure 19)
●
sd_subs_always = 0: subsampling of the first enabled ADC channel only (Figure 20)
The following three figures below show how subsampling is executed by the sequencer. In all of them
ADC cycle means one ADC iteration through all the enabled channels.
Attention
ADC cycle is not the same as sequencer cycle. ADC_SEL is the ADC channel selection;
ADC_ACCESS is an ADC conversion of the currently selected ADC channel; t
ADC
is the configured
ADC start time in the sequencer configuration; t
SUB
is the sequencer period given by Equation 1.
In Figure 18 three ADC channels are enabled --1 (OFE1), 6 (EAFE) and 11 (GPIO2). No subsampling
enabled (sd_subs=0).
In Figure 19 three ADC channels are enabled -- 0 (TIA), 4 (SD2) and 8 (ECGO). Subsampling is
enabled, every second sequencer cycle will trigger the ADC (sd_subs=2) and all enabled ADC
channels are subsampled.
In Figure 20 three ADC channels are enabled
– 0 (TIA), 4 (SD2) and 8 (ECG0). Subsampling is
enabled, every third sequencer cycle will trigger ADC (sd_subs=3) and only the first enabled ADC
channel is subsampled.
