AMD Am186 ES, User Manual, Page: 91 / 192

Interrupt Control Unit 7-3
7.1.1.6 Interrupt Priority
The column titled Overall Priority in Table 7-1 shows the fundamental priority breakdown
for the interrupts at power-on reset. The nonmaskable interrupts 00h through 07h are always
prioritized ahead of the maskable interrupts.
The maskable interrupts can be reprioritized by reconfiguring the PR2–PR0 bits in the
interrupt control registers. The PR2–PR0 bits in all the maskable interrupts are set to priority
level 7 at power-on reset.
7.1.1.7 Software Interrupts
Software interrupts can be initiated by the INT instruction. Any of the 256 possible interrupts
can be initiated by the INT instruction. INT 21h causes an interrupt to the vector located at
00084h in the interrupt vector table. INT FFh causes an interrupt to the vector located at
003FCh in the interrupt vector table.
Software interrupts are not maskable and are not affected by the setting of the IF flag.
7.1.1.8 Software Exceptions
A software exception interrupt occurs when an instruction causes an interrupt due to some
condition in the processor. Interrupt types 00h, 01h, 03h, 04h, 05h, 06h, and 07h are
software exception interrupts.
Software exceptions are not maskable and are not affected by the setting of the IF flag.