AMD Am186 ES, User Manual, Page: 35 / 192

System Overview 3-3
BHE/ADEN Bus High Enable, Am186ES Microcontroller Only
(three-state, output, synchronous)
Address Enable, Am188ES Microcontroller Only
(input, internal pullup)
BHE—During a memory access, this pin and the least-significant
address bit (AD0 or A0) indicate to the system which bytes of the data
bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN
and AD0 pins are encoded as shown.
BHE is asserted during t
1
and remains asserted through t
3
and t
W
. BHE
does not need to be latched. BHE floats during bus hold and reset.
On the Am186ES microcontroller, WLB and WHB implement the
functionality of BHE and AD0 for high and low byte write enables.
BHE/ADEN also signals DRAM refresh cycles when using the
multiplexed address and data (AD) bus. A refresh cycle is indicated
when both BHE/ADEN and AD0 are High. During refresh cycles, the A
bus and the AD bus are not guaranteed to provide the same address
during the address phase of the AD bus cycle. For this reason, the A0
signal cannot be used in place of the AD0 signal to determine refresh
cycles. PSRAM refreshes also provide an additional RFSH signal (see
the MCS3/RFSH pin description on page 3-9).
ADEN—If BHE/ADEN is held High or left floating during power-on reset,
the address portion of the AD bus (AD15–AD0 for the 186 or AO15–
AO8 and AD7–AD0 for the 188) is enabled or disabled during LCS and
UCS bus cycles based on the DA bit in the LMCS and UMCS registers.
If the DA bit is set, the memory address is accessed on the A19–A0
pins. There is a weak internal pullup resistor on BHE/ADEN so no
external pullup is required. This mode of operation reduces power
consumption.
If BHE/ADEN is held Low on power-on reset, the AD bus drives both
addresses and data, regardless of the DA bit setting. The pin is sampled
on the rising edge of RES. (S6 and UZI also assume their normal
functionality in this instance. See Table 3-1 on page 13.)
Note: On the Am188ES microcontroller, AO15–AO8 are driven during
the t
2
–t
4
bus cycle, regardless of the setting of the DA bit in the UMCS
and LMCS registers.
CLKOUTA Clock Output A (output, synchronous)
This pin supplies the internal clock to the system. Depending on the
value of the system configuration register (SYSCON), CLKOUTA
operates at either the crystal input frequency (X1), the power-save
frequency, or is three-stated. CLKOUTA remains active during reset and
bus hold conditions.
BHE AD0 Type of Bus Cycle
0 0 Word Transfer
0 1 High Byte Transfer (Bits 15–8)
1 0 Low Byte Transfer (Bits 7–0)
1 1 Refresh