AMD Am186 ES, User Manual, Page: 143 / 192

DMA Controller 9-11
9.4 DMA REQUESTS
Data transfers can be either source or destination synchronized—either the source of the
data or the destination of the data can request the data transfer. DMA transfers can also
be unsynchronized (i.e., the transfer takes place continually until the correct number of
transfers has occurred).
During source synchronized or unsynchronized transfers, the DMA channel can begin a
transfer immediately after the end of the previous DMA transfer, and a complete transfer
can occur every two bus cycles or eight clock cycles (assuming no wait states).
When destination synchronization is performed, data is not fetched from the source address
until the destination device signals that it is ready to receive it. When destination
synchronized transfers are requested, the DMA controller relinquishes control of the bus
after every transfer. If no other bus activity is initiated, another DMA cycle begins after two
processor clocks. This gives the destination device time to remove its request if another
transfer is not desired.
When the DMA controller relinquishes the bus during destination synchronized transfers,
the CPU can initiate a bus cycle. As a result, a complete bus cycle is often inserted between
destination-synchronized transfers. Table 9-3 shows the maximum DMA transfer rates
based on the different synchronization strategies.
Table 9-3 Maximum DMA Transfer Rates
Synchronization Type
Maximum DMA
Transfer Rate (Mbytes/sec)
40 MHz 33 MHz 25 MHz 20 MHz
Unsynchronized 10 8.25 6.25 5
Source Synch 10 8.25 6.25 5
Destination Synchronized
(CPU needs bus) 6.6 5.5 4.16 3.3
Destination Synchronized
(CPU does not need bus) 8 6.6 5 4