AMD Am186 ES, User Manual, Page: 42 / 192

System Overview 3-10
An NMI transition from Low to High is latched and synchronized
internally, and it initiates the interrupt at the next instruction boundary.
To guarantee that the interrupt is recognized, the NMI pin must be
asserted for at least one CLKOUTA period.
PCS1–PCS0 (PCS1/PIO17, PCS0/PIO16)
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory access is in progress
to the corresponding region of the peripheral memory block (either I/O
or memory address space). The base address of the peripheral memory
block is programmable. PCS3–PCS0 are held High during a bus hold
condition. They are also held High during reset.
Unlike the UCS and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus. Note also that each peripheral chip select
asserts over a 256-byte address range, which is twice the address range
covered by peripheral chip selects in earlier generations of the 80C186
and 80C188 microcontrollers.
PCS2/CTS1/ENRX1/PIO18
Peripheral Chip Select 2 (output, synchronous)
Clear-to-Send 1 (input, asynchronous)
Enable-Receiver-Request 1 (input, asynchronous)
PCS2—This pin provides the Peripheral Chip Select 2 signal to the
system when hardware flow control is not enabled for asynchronous
serial port 1. The PCS2 signal indicates to the system that a memory
access is in progress to the corresponding region of the peripheral
memory block (either I/O or memory address space). The base address
of the peripheral memory block is programmable. PCS2 is held High
during a bus hold or reset condition.
Unlike the UCS and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus. Note also that each peripheral chip select
asserts over a 256-byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and 80C188
microcontrollers.
CTS1—This pin provides the Clear to Send signal for asynchronous
serial port 1 when the ENRX1 bit in the AUXCON register is 0 and
hardware flow control is enabled for the port (FC bit in the serial port 1
control register is set). The CTS1 signal gates the transmission of data
from the associated serial port transmit register. When CTS1 is
asserted, the transmitter will begin transmission of a frame of data, if
any is available. If CTS1 is deasserted, the transmitter holds the data
in the serial port transmit register. The value of CTS1 is checked only
at the beginning of the transmission of the frame.
ENRX1—This pin provides the Enable Receiver Request for
asynchronous serial port 1 when the ENRX1 bit in the AUXCON register
is 1 and hardware flow control is enabled for the port (FC bit in the serial
port 1 control register is set). The ENRX1 signal enables the receiver
for the associated serial port.