AMD Am186 ES, User Manual, Page: 39 / 192

System Overview 3-7
INTA0—When the microcontroller interrupt control unit is operating in
cascade mode, this pin indicates to the system that the microcontroller
needs an interrupt type to process the interrupt request on INT0. The
peripheral issuing the interrupt request must provide the microcontroller
with the corresponding interrupt type.
PWD—If pulse width demodulation is enabled, PWD processes a signal
through the Schmitt trigger. PWD is used internally to drive TIMERIN0
and INT2, and PWD is inverted internally to drive TIMERIN1 and INT4.
If INT2 and INT4 are enabled and timer 0 and timer 1 are properly
configured, the pulse width of the alternating PWD signal can be
calculated by comparing the values in timer 0 and timer 1.
In PWD mode, the signals TIMERIN0/PIO11, TIMERIN1/PIO0, and
INT4/PIO30 can be used as PIOs. If they are not used as PIOs they
are ignored internally. The level of INT2/INTA0/PWD/PIO31 is reflected
in the PIO data register for PIO31 as if it was a PIO.
INT3/INTA1/IRQ Maskable Interrupt Request 3 (input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pin indicates to the microcontroller that an interrupt request
has occurred. If the INT3 pin is not masked, the microcontroller then
transfers program execution to the location specified by the INT3 vector
in the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can be edge-
triggered or level-triggered. To guarantee interrupt recognition, the
requesting device must continue asserting INT3 until the request is
acknowledged. INT3 becomes INTA1 when INT1 is configured in
cascade mode.
INTA1—When the microcontroller interrupt control unit is operating in
cascade mode, this pin indicates to the system that the microcontroller
needs an interrupt type to process the interrupt request on INT1. The
peripheral issuing the interrupt request must provide the microcontroller
with the corresponding interrupt type.
IRQ—When the microcontroller interrupt control unit is operating as a
slave to an external master interrupt controller, this pin lets the
microcontroller issue an interrupt request to the external master
interrupt controller.
INT4/PIO30 Maskable Interrupt Request 4 (input, asynchronous)
This pin indicates to the microcontroller that an interrupt request has
occurred. If the INT4 pin is not masked, the microcontroller then
transfers program execution to the location specified by the INT4 vector
in the microcontroller interrupt vector table.
Interrupt requests are synchronized internally, and can be edge-
triggered or level-triggered. To guarantee interrupt recognition, the
requesting device must continue asserting INT4 until the request is
acknowledged.
When pulse width demodulation mode is enabled, the INT4 signal is
used internally to indicate a High-to-Low transition on the PWD signal.