AMD Am186 ES, User Manual, Page: 67 / 192

Peripheral Control Block 4-7
4.1.5 System Configuration Register
(SYSCON, Offset F0h)
The format of the system configuration register is shown in Figure 4-5.
Figure 4-5 System Configuration Register
The value of the SYSCON register at reset is 0000h.
Bit 15: Enable Power-Save Mode (PSEN)—When set to 1, enables power-save mode
and divides the internal operating clock by the value in F2–F0. PSEN is automatically
cleared when an external interrupt, including those generated by on-chip peripheral
devices, occurs. The value of the PSEN bit is not restored by the execution of an IRET
instruction. Software interrupts (INT instruction) and exceptions do not clear the PSEN bit,
and interrupt service routines for these conditions should do so, if desired. This bit is 0 after
processor reset.
Bit 14: MCS0 Only Mode Bit (MCSBIT)—This bit controls the MCS0 only mode. When
set to 0, the middle chip selects operate normally. When set to 1, MCS0 is active over the
entire MCS range. This bit is 0 after processor reset.
Bit 13: Data Strobe Mode of DEN Enable (DSDEN)—This bit enables the data strobe
timings on the DEN pin. When this bit is set to 1, data strobe bus mode is enabled, and the
DS timing for reads and writes is identical to the normal read cycle DEN timing. When this
bit is set to 0, the DEN timing for both reads and writes is normal. The DEN pin is renamed
DS in data strobe bus mode. This bit is 0 after processor reset.
During the bus cycle in which the DSDEN bit of the SYSCON register is written, the timing
of the DEN/DS pin is slightly different from normal. When a 1 is written to the DSDEN bit
(which previously contained a 0), the falling edge of DEN/DS occurs during PH2 of T
1
as
it does during a normal write cycle, but the rising edge occurs during PH1 of T
4
in
conformance with the data strobe timing. All writes after this have the normal data strobe
timing until the DSDEN bit is reset.
When a 0 is written to the DSDEN bit (which previously contained a 1), the falling edge of
DEN/DS occurs during PH2 of T
2
as it does with the data strobe timing, but the rising edge
occurs during PH2 of T
4
in conformance with normal write cycle timing. All writes after this
have the normal write cycle timing until the DSDEN bit is set again.
Bit 12: Pulse Width Demodulation Mode Enable (PWD)—This bit enables pulse width
demodulation mode. When this bit is set to 1, pulse width demodulation is enabled. When
this bit is set to 0, pulse width demodulation is disabled. This bit is 0 after processor reset.
Bit 11: CLKOUTB Output Frequency (CBF)—When set to 1, CLKOUTB follows the crystal
input (PLL) frequency. When set to 0, CLKOUTB follows the internal processor frequency
(after the clock divisor). This bit is 0 after processor reset.
15
7 0
0 0 0 0 0
CBD
CAF
CAD
F1
F0 F2
PSEN
CBF
MCSBIT
DSDEN
PWD