AMD Am186 ES, User Manual, Page: 86 / 192

Refresh Control Unit 6-2
6.1.2 Clock Prescaler Register
(CDRAM, Offset E2h)
Figure 6-2 Clock Prescaler Register
The CDRAM register is undefined on reset.
Bits 15–9: Reserved—Read back as 0.
Bits 8–0: Refresh Counter Reload Value (RC8–RC0)—Contains the value of the desired
clock count interval between refresh cycles. The counter value should not be set to less
than 18 (12h), otherwise there would never be sufficient bus cycles available for the
processor to execute code.
In power-save mode, the refresh counter value must be adjusted to take into account the
reduced processor clock rate.
6.1.3 Enable RCU Register
(EDRAM, Offset E4h)
Figure 6-3 Enable RCU Register
The EDRAM register is set to 0000h on reset.
Bit 15: Enable RCU (EN)—Enables the refresh counter unit and changes MCS3 to RFSH
when set to 1. Clearing the EN bit at any time clears the refresh counter and stops refresh
requests, but it does not reset the refresh address. This bit is 0 after processor reset.
Bits 14–9: Reserved—Read back as 0.
Bits 8–0: Refresh Count (T8–T0)—This read-only field contains the current value of the
down counter that triggers refresh requests.
15
7 0
0 0 0 0 0 0
RC8–RC0
0
15
7 0
0 0 0 0 0
T8–T0
0
EN