AMD Am186 ES, User Manual, Page: 142 / 192

DMA Controller 9-10
9.3.7 DMA Source Address Low Register (Low Order Bits)
(D0SRCL, Offset C0h, D1SRCL, Offset D0h)
Figure 9-7 shows the DMA Source Address Low register. The sixteen bits of this register
are combined with the four bits of the DMA Source Address High register (see Figure 9-6)
to produce a 20-bit source address.
Figure 9-7 DMA Source Address Low Register
The value of D0SRCL and D1SRCL at reset is undefined.
Bits 15–0: DMA Source Address Low (DSA15–DSA0)—These bits are driven onto A15–
A0 during the read phase of a DMA transfer.
15
7 0
DSA15–DSA0