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DMA Controller

9-2

Figure 9-1

DMA Unit Block Diagram

Source Address Ch. 1

Source Address Ch. 0

 20-bit Adder/Subtractor 

DMA 

Control 

Logic

Request 

Selection 

Logic

Adder Control 

Logic

20

20

 Channel Control Register 1
 Channel Control Register 0

16

DRQ1/Serial Port

DRQ0/Serial Port

Internal Address/Data Bus

Timer Request

Interrupt
Request

Transfer Counter Ch. 1

Destination Address Ch. 1

Destination Address Ch. 0

Transfer Counter Ch. 0

Summary of Contents for Am186 ES

Page 1: ...Am186 ES and Am188 ES User s Manual...

Page 2: ...resentations or warranties of any kind including but not limited to any implied warranty of merchantability or fitness for a particular purpose AMD products are not authorized for use as critical comp...

Page 3: ...o lpd support amd com Corporate Applications Hotline 800 222 9323 toll free for U S 44 0 1276 803 299 U K and Europe hotline World Wide Web Home Page and FTP Site To access the AMD home page go to htt...

Page 4: ...iv...

Page 5: ...HAPTER 3 SYSTEM OVERVIEW 3 1 PIN DESCRIPTIONS 3 1 3 1 1 Pins That Are Used by Emulators 3 19 3 2 BUS OPERATION 3 20 3 3 BUS INTERFACE UNIT 3 23 3 3 1 Nonmultiplexed Address Bus 3 23 3 3 2 Static Bus S...

Page 6: ...ller Reset Conditions 7 9 7 2 MASTER MODE OPERATION 7 10 7 2 1 Fully Nested Mode 7 10 7 2 2 Cascade Mode 7 11 7 2 3 Special Fully Nested Mode 7 12 7 2 4 Operation in a Polled Environment 7 12 7 2 5 En...

Page 7: ...T0CMPA Offset 52h T0CMPB Offset 54h T1CMPA Offset 5Ah T1CMPB Offset 5Ch T2CMPA Offset 62h 8 7 CHAPTER 9 DMA CONTROLLER 9 1 OVERVIEW 9 1 9 2 DMA OPERATION 9 1 9 3 PROGRAMMABLE DMA REGISTERS 9 3 9 3 1 D...

Page 8: ...INS 11 1 OVERVIEW 11 1 11 2 PIO MODE REGISTERS 11 3 11 2 1 PIO Mode 1 Register PIOMODE1 Offset 76h 11 3 11 2 2 PIO Mode 0 Register PIOMODE0 Offset 70h 11 3 11 3 PIO DIRECTION REGISTERS 11 4 11 3 1 PIO...

Page 9: ...MCS Auxiliary Register 5 10 Figure 5 5 Peripheral Chip Select Register 5 12 Figure 6 1 Memory Partition Register 6 1 Figure 6 2 Clock Prescaler Register 6 2 Figure 6 3 Enable RCU Register 6 2 Figure...

Page 10: ...9 12 Figure 9 9 Destination Synchronized DMA Transfers 9 13 Figure 10 1 DCE DTE Protocol 10 2 Figure 10 2 CTS RTR Protocol 10 3 Figure 10 3 Serial Port Control Register 10 5 Figure 10 4 Serial Port 0...

Page 11: ...0 Wait State Encoding 5 13 Table 6 1 Watchdog Timer COUNT Settings 6 4 Table 6 2 Watchdog Timer Duration 6 4 Table 7 1 Am186ES and Am188ES Microcontroller Interrupt Types 7 4 Table 7 2 Interrupt Contr...

Page 12: ...Table of Contents xii...

Page 13: ...and Am188ES microcontrollers INTENDED AUDIENCE This manual is intended for computer hardware and software engineers and system architects who are designing or are considering designing systems based o...

Page 14: ...tructionincludedinthe Am186 and Am188 Family Instruction Set 19255 FusionE86SM Catalog Provides information on tools that speed an E86 family embedded product to market Includes products from expert s...

Page 15: ...trollers offer application specific features that can enhance the system functionality of the Am186EM and Am188EM microcontrollers Upgrading to the Am186ES and Am188ES microcontrollers is an attractiv...

Page 16: ...r operates at the clock input frequency On the Am186ES microcontroller 8 bit or 16 bit memory and I O static bus option n Enhanced integrated peripherals provide increased functionality while reducing...

Page 17: ...ck divider n Software compatible withthe80C186 and80C188 microcontrollerswith widely available native development tools applications and system software n A compatible evolution of the Am186 EM and Am...

Page 18: ...Count A Registers 16 Bit Count Registers 20 Bit Destination Pointers 20 Bit Source Pointers Control Registers Control Registers Control Registers 0 1 2 0 1 Max Count B Registers Refresh Control Unit...

Page 19: ...Registers 16 Bit Count Registers 20 Bit Destination Pointers 20 Bit Source Pointers Control Registers Control Registers Control Registers 0 1 2 0 1 Max Count B Registers Refresh Control Unit Control...

Page 20: ...nd disabling Figure 1 3 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost Figure 1 3 Basic Functional System Design 1 3...

Page 21: ...nterface requires the following n The processor A19 A0 bus connects to the memory address inputs n The AD bus connects directly to the data inputs outputs n The chip selects connect to the memory chip...

Page 22: ...Features and Performance 1 8...

Page 23: ...icular locations within a segment The addressing modeselectsthespecificregisters for operandandaddress calculations Stack Pointer Register All stack operations POP POPA POPF PUSH PUSHA PUSHF utilize t...

Page 24: ...er F Bits 15 12 Reserved Bit 11 Overflow Flag OF Set if the signed result cannot be expressed within the number of bits in the destination operand cleared otherwise Bit 10 Direction Flag DF Causes str...

Page 25: ...s of a 16 bit segment value and a 16 bit offset The offset is the number of bytes from the beginning of the segment the segment address to the data or instruction that is being accessed The processor...

Page 26: ...addressing I O space Figure 2 4 Memory and I O Space 2 4 INSTRUCTION SET The instruction set used by the Am186ES and Am188ES microcontrollers is identical to the 80C186 188 instruction set An instruct...

Page 27: ...C Complement carry flag CMP Compare byte or word CMPS Compare byte or word string CWD Convert word to doubleword DAA Decimal adjust for addition DAS Decimal adjust for subtraction DEC Decrement byte o...

Page 28: ...erflow JNP JPO Jump if not parity parity odd JNS Jump if not sign JO Jump if overflow JP JPE Jump if parity parity even JS Jump if sign LAHF Load AH register from flags LDS Load pointer using DS LEA L...

Page 29: ...Return from procedure ROL Rotate left byte or word ROR Rotate right byte or word SAHF Store AH register in flags SF ZF AF PF and CF SAL Shift left arithmetic byte or word SAR Shift right arithmetic b...

Page 30: ...s implied by the addressing mode used see Table 2 2 Table 2 2 Segment Register Selection Rules 2 6 DATA TYPES The Am186ES and Am188ES microcontrollers directly support the following data types n Integ...

Page 31: ...gure 2 5 Supported Data Types 7 0 Signed Byte Magnitude Magnitude 7 0 MSB Unsigned Byte Signed Word Magnitude MSB 1 0 Magnitude MSB 3 2 1 0 Signed Quad Word Magnitude MSB 63 48 47 32 31 16 15 0 Unsign...

Page 32: ...registers 3 Index contents of either the SI or DI index registers Any carry from the 16 bit addition is ignored Eight bit displacements are sign extended to 16 bit values Combinations of the above th...

Page 33: ...ta bus AD15 AD0 on the 186 or AO15 AO8 and AD7 AD0 on the 188 During a bus hold or reset condition the address bus is in a high impedance state AD15 AD8 Address and Data Bus Am186ES Microcontroller On...

Page 34: ...re three stated during t2 t3 and t4 During a bus hold or reset condition the address and data bus is in a high impedance state During a power on reset the address and data bus pins AD15 AD0 for the 18...

Page 35: ...ription on page 3 9 ADEN If BHE ADEN is held High or left floating during power on reset the address portion of the AD bus AD15 AD0 for the 186 or AO15 AO8 and AD7 AD0 for the 188 is enabled or disabl...

Page 36: ...RX0 bit in the AUXCON register is 1 and hardware flow control is enabled for the port FC bit in the serial port 0 control register is set The ENRX0 signal enables the receiver for the associated seria...

Page 37: ...controller to the system ground HLDA Bus Hold Acknowledge output synchronous This pin is asserted High to indicate to an external bus master that the microcontroller has relinquished control of the lo...

Page 38: ...has occurred If INT1 is not masked the microcontroller transfers program execution to the location specified by the INT1 vector in the microcontroller interrupt vector table Interrupt requests are syn...

Page 39: ...vector in the microcontroller interrupt vector table Interrupt requests are synchronized internally and can be edge triggered or level triggered To guarantee interrupt recognition the requesting devi...

Page 40: ...pin indicates to the system that a memory access is in progress to the corresponding region of the midrange memory block The base address and size of the mid range memory block are programmable On th...

Page 41: ...equate deassertion period to ensure that overall auto refresh cycle time is met This signal functions like the RFSH signal in the Am186EM and Am188EM microcontrollers except that the DRAM row address...

Page 42: ...signal indicates to the system that a memory access is in progress to the corresponding region of the peripheral memory block either I O or memory address space The base address of the peripheral mem...

Page 43: ...e RTS1 bit in the AUXCON register is 0 and hardware flow control is enabled for the port FC bit in the serial port 1 control register isset TheRTR1signal isassertedwhentheassociated serial port receiv...

Page 44: ...32 individually programmable I O pins Each PIO can be programmed with the following attributes PIO function enabled disabled direction input output and weak pullup or pulldown The pins that are multip...

Page 45: ...S Normal operation 3 6 SRDY Normal operation 4 7 1 A17 Normal operation 3 8 1 A18 Normal operation 3 9 1 A19 Normal operation 3 10 TMROUT0 Input with pulldown 11 TMRIN0 Input with pullup 12 DRQ0 INT5...

Page 46: ...0 INT5 12 Input with pullup DRQ1 INT6 13 Input with pullup DT R 4 Normal operation 3 INT2 INTA0 PWD 31 Input with pullup INT4 30 Input with pullup MCS0 14 Input with pullup MCS1 15 Input with pullup M...

Page 47: ...o signify a DRAM refresh bus cycle The use of RFSH2 ADEN to signal a refresh is not valid when PSRAM mode is selected Instead the MCS3 RFSH signal is provided to the PSRAM ADEN If RFSH2 ADEN is held H...

Page 48: ...ternal pullup S6 During the second and remaining periods of a cycle t2 t3 and t4 this pin is asserted High to indicate a DMA initiated bus cycle During a bus hold or reset condition S6 floats LOCK Thi...

Page 49: ...nabled The TMRIN0 PIO11 pin can be used as a PIO when pulse width demodulation mode is enabled TMRIN1 PIO0 Timer Input 1 input synchronous edge sensitive This pin supplies a clock or control signal to...

Page 50: ...progress by ORing it with bits 15 10 of the address and data bus AD15 AD10 on the 186 and AO15 AO10 on the 188 UZI is the logical AND of the inverted A19 A16 bits It asserts in the first period of a b...

Page 51: ...nnect the source to the X1 pin and leave the X2 pin unconnected X2 Crystal Output output This pin and the X1 pin provide connections for a fundamental mode or third overtone parallel resonant crystal...

Page 52: ...ting at high clock rates On the Am188ES microcontroller the address is driven on A015 A08 during the data portion of the bus cycle regardless of the setting of the DA bits If the ADEN pin is pulled Lo...

Page 53: ...ocontroller Read and Write with Address Bus Disable In Effect CLKOUTA t1 t2 t3 t4 AD15 AD0 Read Data AD15 AD0 Write LCS or UCS Address Data Address Address Phase Data Phase A19 A0 Address MCSx PCSx CL...

Page 54: ...Write with Address Bus Disable In Effect CLKOUTA t1 t2 t3 t4 AD7 AD0 Read Data AO15 AO8 Read or Write AD7 AD0 Write Address Address Data Address Address Phase Data Phase A19 A0 Address LCS or UCS MCS...

Page 55: ...188ES Microcontrollers Data Sheet order 20002 3 3 1 Nonmultiplexed Address Bus The nonmultiplexed address bus A19 A0 is valid one half CLKOUTA cycle in advance of the address on the AD bus When used i...

Page 56: ...on page 5 6 The PSRAM feature is disabled on CPU reset In addition to the LCS timing changes for PSRAM precharge the PSRAM devices also require periodic refresh of all internal row addresses to retai...

Page 57: ...during power on reset by an on chip power on reset POR circuit 3 4 2 Crystal Driven Clock Source The internal oscillator circuit of the microcontroller is designed to function with a parallel resonant...

Page 58: ...rting amplifier these values need to be offset with the larger load on the output X2 Equal values of these loads tend to balance the poles of the inverting amplifier The characteristics of the inverti...

Page 59: ...power save frequency Individual drive enable bits allow selective enabling of just one or both of these clock outputs 3 4 5 Power Save Operation The power save mode reduces power consumption and heat...

Page 60: ...System Overview 3 28...

Page 61: ...s Code written in this manner will run correctly on the Am188ES microcontroller and on the Am186ES microcontroller Unaligned reads and writes to the PCB result in unpredictable behavior on both the Am...

Page 62: ...t register C8h 9 6 INT1 control register 3Ah 7 14 DMA 0 destination address high register C6h 9 7 INT0 control register 38h 7 14 DMA 0 destination address low register C4h 9 8 DMA1 INT6 interrupt cont...

Page 63: ...tion information for the control block the Peripheral Control Block Relocation register contains a bit that places the interrupt controller into either slave mode or master mode At reset the Periphera...

Page 64: ...dress data bus during reset For example the Reset Configuration register could be used to provide the software with the position of a configuration switch in the system Using weak externalpullupand pu...

Page 65: ...4 3 Processor Release Level Register Bits 15 8 Processor Release Level PRL This byte returns the current release level of the processor as well as the identification of the family member The Am186ES...

Page 66: ...bit is 0 the RTR0 RTS0 pin is configured as RTR0 This bit is 0 after processor reset Bit 2 LCS Data Bus Size LSIZ Am186ES microcontroller only This bit determines the width of the data bus for accesse...

Page 67: ...ng for both reads and writes is normal The DEN pin is renamed DS in data strobe bus mode This bit is 0 after processor reset During the bus cycle in which the DSDEN bit of the SYSCON register is writt...

Page 68: ...Read back as 0 Bits 2 0 Clock Divisor Select F2 F0 Controls the division factor when Power Save mode is enabled F2 F0 is 000b after processor reset Allowable values are as follows 4 2 INITIALIZATION...

Page 69: ...w Memory Chip Select LMCS Undefined Serial Port 1 Control SP1CT 0000h Serial port interrupts disabled no loopback no break BRKVAL low no parity word length 7 1 stop bit transmitter and receiver disabl...

Page 70: ...e triggered priority 7 DMA0 Interrupt Control INT5 DMA0CON 000Fh DMA0 interrupts masked edge triggered priority 7 Timer Interrupt Control TCUCON 000Fh Timer interrupts masked edge triggered priority 7...

Page 71: ...0h is used to program the Upper Memory Chip Select UCS The LMCS register offset A2h is used to program the Lower Memory Chip Select LCS The Midrange Memory Chip Selects MCS3 MCS0 are programmed throug...

Page 72: ...region is programmable Zero wait states to 15 wait states can be inserted for the PCS3 PCS0 peripheral chip selects Zero wait states to three wait states can be inserted for all other chip selects Eac...

Page 73: ...s chip selects or PIOs This means that if these chip selects are enabled by a write to the MMCS and MPCS for the MCS chip selects or by a write to the PACS and MPCS registers for the PCS chip selects...

Page 74: ...ip Select Register The value of the UMCS register at reset is F03Bh Bit 15 Reserved Set to 1 Bits 14 12 Lower Boundary LB2 LB0 The LB2 LB0 bits define the lower bound of the memory access through the...

Page 75: ...egardless of the DA setting This configures AD15 AD0 to be enabled regardless of the setting of DA If BHE ADEN on the 186 or RFSH2 ADEN on the 188 is High on the rising edge of RES then DA in the Uppe...

Page 76: ...15 Reserved Set to 0 Bits 14 12 Upper Boundary UB2 UB0 The UB2 UB0 bits define the upper boundary of the memory accessed through the LCS chip select Because of the timing requirements of the LCS outp...

Page 77: ...en DA in the UMCS register and DA in the LMCS register control the AD15 AD0 disabling See the descriptions of the BHE ADEN and RFSH2 ADEN pins in Chapter 3 Bit 6 PSRAM Mode Enable PSE The PSE bit is u...

Page 78: ...ng is delayed for a half cycle later than that for UCS and LCS The Midrange Memory Chip Selects are configured by the MMCS register Figure 5 3 Figure 5 3 Midrange Memory Chip Select Register The value...

Page 79: ...y is required If R2 is set to 1 external ready is ignored In each case the processor also uses the value of the R1 R0 bits to determine the number of wait states to insert Bits 1 0 Wait State Value R1...

Page 80: ...pins to activate No corresponding access to the PACS register is required to activate the PCS6 PCS5 pins as addresses Figure 5 4 PCS and MCS Auxiliary Register The value of the MPCS register at reset...

Page 81: ...PCS outputs are active for memory bus cycles When MS is set to 0 the PCS outputs are active for I O bus cycles Bits 5 3 Reserved Set to 1 Bit 2 Ready Mode R2 This bit applies only to the PCS6 PCS5 ch...

Page 82: ...2 When the PCS6 PCS5 pins are chip selects the MPCS register also determines whether PCS chip selects are active during memory or I O bus cycles and specifies the ready and wait states for the PCS6 PC...

Page 83: ...set to 1 In each case the processor also uses the value of the R3 and R1 R0 bits to determine the number of wait states to insert The ready mode for PCS6 PCS5 is configured through the MPCS register...

Page 84: ...Chip Select Unit 5 14...

Page 85: ...nerated indicating a bus hold condition then the microcontroller deactivates the HLDA pin in order to perform a refresh cycle The circuit external bus master must remove the HOLD signal for at least o...

Page 86: ...efresh counter value must be adjusted to take into account the reduced processor clock rate 6 1 3 Enable RCU Register EDRAM Offset E4h Figure 6 3 Enable RCU Register The EDRAM register is set to 0000h...

Page 87: ...ey as long as they do not access the WDTCON register The current count should be reset before modifying the WDT timeout period to ensure that an immediate WDT timeout does not occur Figure 6 4 Watchdo...

Page 88: ...the WDT timeout period for a 40 MHz processor with the COUNT field set to 20h Duration 224 cycles 40 000 000 Hz 16 777 216 cycles 40 000 000 cycles second 4194 seconds Setting more than one bit in th...

Page 89: ...gered or level triggered INT6 and INT5 are edge triggered only In addition INT0 and INT1 can be configured in cascade mode for use with an external 82C59A compatible interrupt controller When INT0 is...

Page 90: ...ocontrollers provide two methods for masking and unmasking the maskable interrupt sources Each interrupt source has an interrupt control register that contains a mask bit specific to that interrupt In...

Page 91: ...e interrupts can be initiated by the INT instruction Any of the 256 possible interrupts can be initiated by the INT instruction INT 21h causes an interrupt to the vector located at 00084h in the inter...

Page 92: ...EOI Type Overall Priority Related Instructions Notes Divide Error Exception 00h 00h N A 1 DIV IDIV 1 Trace Interrupt 01h 04h N A 1A All 2 Nonmaskable Interrupt NMI 02h 08h N A 1B Breakpoint Interrupt...

Page 93: ...shifted left 2 bit positions multiplied by 4 to generate the index into the interrupt vector table 7 1 2 4 Interrupt Servicing A valid interrupt transfers execution to a new program location based on...

Page 94: ...ty breakdown 7 1 3 2 Maskable Hardware Interrupt Priority Beginning with interrupt type 8 the timer 0 interrupt the maskable hardware interrupts have both an overall priority see Table 7 1 and a progr...

Page 95: ...nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted Although NMI is the highest priority interrupt source it does not participate in the priority resolution...

Page 96: ...rrupt vector table When the internal interrupt controller is supplying the interrupt type no interrupt acknowledge bus cycles are generated The only external indication that an interrupt is being serv...

Page 97: ...et to 1 This places all sources at the lowest priority level 7 3 All level triggered mode LTM bits are reset to 0 resulting in edge triggered mode 4 All interrupt in service bits are reset to 0 5 All...

Page 98: ...modes of interrupt controller operation are fully nested mode cascade mode special fully nested mode and polled mode 7 2 1 Fully Nested Mode In fully nested mode seven pins are used as direct interru...

Page 99: ...INT0 is an interrupt input interfaced to one 82C59A and INT2 INTA0 serves as the dedicated interrupt acknowledge signal to that peripheral INT1 and INT3 INTA1 are also interfaced to an 82C59A Each in...

Page 100: ...t controller can be used in polled mode if interrupts are not desired When polling interrupts are disabled and software polls the interrupt controller as required The interrupt controller is polled by...

Page 101: ...in Master Mode Offset Register Mnemonic Register Name Associated Pins Comments 38h I0CON INT0 Control INT0 3Ah I1CON INT1 Control INT1 3Ch I2CON INT2 Control INT2 3Eh I3CON INT3 Control INT3 40h I4CON...

Page 102: ...de mode for INT0 or INT1 Bit 4 Level Triggered Mode LTM This bit determines whether the microcontroller interprets an INT0 or INT1 interrupt request as edge or level sensitive A 1 in this bit configur...

Page 103: ...el sensitive A 1 in this bit configures INT2 or INT3 as an active High level sensitive interrupt A 0 in this bit configures INT2 or INT3 as a Low to High edge triggered interrupt In either case INT2 o...

Page 104: ...ode LTM This bit determines whether the microcontroller interprets an INT4 interrupt request as edge or level sensitive A 1 in this bit configures INT4 as an active High level sensitive interrupt A 0...

Page 105: ...configure these pins as DMA requests or external interrupts Figure 7 7 Timer DMA Interrupt Control Registers The value of TCUCON DMA0CON and DMA1CON at reset is 000Fh Bits 15 4 Reserved Set to 0 Bit...

Page 106: ...01Fh Bits 15 5 Reserved Set to 0 Bit 4 Reserved Set to 1 Bit 3 Mask MSK This bit determines whether the serial port can cause an interrupt A 1 in this bit masks this interrupt source preventing the se...

Page 107: ...s executed Time critical software such as interrupt handlers can modify this bit directly to inhibit DMA transfers Because of the function of this register as an interrupt request register for the tim...

Page 108: ...ove the interrupt request Figure 7 10 Interrupt Request Register The REQST register is undefined on reset Bits 15 11 Reserved Bit 10 Serial Port 0 Interrupt Request SP0 This bit indicates the interrup...

Page 109: ...state of the timer interrupts This bit is the logical OR of the timer interrupt requests When set to a 1 this bit indicates that the timer control unit has an interrupt pending The interrupt status re...

Page 110: ...t In Service SP1 This bit indicates the in service state of the serial port 1 Bits 8 4 Interrupt In Service INT4 INT0 These bits indicate the in service state of the corresponding INT pin Bit 3 DMA Ch...

Page 111: ...uired for a maskable interrupt source to generate an interrupt Maskable interrupts with programmable priority values that are numerically higher than this field are masked The possible values are zero...

Page 112: ...SK register is set to 07FDh on reset Bits 15 11 Reserved Bit 10 Serial Port 0 Interrupt Mask SP0 When set to 1 this bit indicates that the serial port 0 interrupt is masked Bit 9 Serial Port 1 Interru...

Page 113: ...read the current interrupt is acknowledged and the next interrupt takes its place in the Poll register This is a read only register Figure 7 14 Poll Status Register Bit 15 Interrupt Request IREQ Set...

Page 114: ...ure 7 15 Poll Register Bit 15 Interrupt Request IREQ Set to 1 if an interrupt is pending When this bit is set to 1 the S4 S0 field contains valid data Bits 14 5 Reserved Set to 0 Bits 4 0 Poll Status...

Page 115: ...16 shows example code for a specific EOI reset See Table 7 1 on page 7 4 for specific EOI values Figure 7 16 Example EOI Assembly Code Figure 7 17 End of Interrupt Register Bit15 Non SpecificEOI NSPE...

Page 116: ...controller operation The programmer must assign correct priorities and initialize interrupt control registers before enabling interrupts 7 4 1 Slave Mode Interrupt Nesting Slave mode operation allows...

Page 117: ...18 Timer and DMA Interrupt Control Registers These registers are set to 000Fh on reset Bits 15 4 Reserved Set to 0 Bit 3 Mask MSK This bit determines whether the interrupt source can cause an interru...

Page 118: ...timers Figure 7 19 Interrupt Status Register The INTSTS register is set to 0000h on reset Bit 15 DMA Halt DHLT When set to 1 halts any DMA activity Automatically set to 1 when nonmaskable interrupts o...

Page 119: ...s an interrupt The bit is reset during the internally generated interrupt acknowledge Figure 7 20 Interrupt Request Register The REQST register is set to 0000h on reset Bits 15 6 Reserved Bits 5 4 Tim...

Page 120: ...rupt In Service Register The INSERV register is set to 0000h on reset Bits 15 6 Reserved Bits 5 4 Timer 2 Timer 1 Interrupt In Service TMR2 TMR1 When set to 1 these bits indicate that the correspondin...

Page 121: ...etermines the minimum priority which is required for a maskable interrupt source to generate an interrupt Maskable interrupts with programmable priority values that are numerically higher than this fi...

Page 122: ...ed Bits 5 4 Timer 2 Timer 1 Interrupt Mask TMR2 TMR1 These bits indicate the state of the mask bit of the Timer Interrupt Control register and when set to a 1 indicate which source has its interrupt r...

Page 123: ...t The command is executed by writing the correct value in the Specific EOI register at offset 22h Figure 7 24 Specific End of Interrupt Register The EOI register is undefined on reset Bits 15 3 Reserv...

Page 124: ...set into the interrupt vector table Figure 7 25 Interrupt Vector Register The INTVEC register is undefined on reset Bits 15 8 Reserved Read as 0 Bits 7 3 Interrupt Type T4 T0 Sets the five most signif...

Page 125: ...ocontroller to support the detection of rising and falling edges on the PWD input pin INT2 INTA0 PWD and to enable either timer 0 when the signal is High or timer 1 when the signal is Low The INT4 TMR...

Page 126: ...e is reached If the timer is programmed to use both of its maximum count registers the output pin creates a waveform by indicating which maximum count register is currently in control The duty cycle a...

Page 127: ...s serviced the interrupt request will still be present Bit 12 Register in Use Bit RIU When the maxcount compare A register is being used for comparison to the timer count value this bit is set to 0 Wh...

Page 128: ...ts the count register to zero and starts counting again against maxcount compare A In this case mlaxcount compare B is not used Bit 0 Continuous Mode Bit CONT When set to 1 CONT causes the associated...

Page 129: ...When INT is set to 1 an interrupt request is generated when the count register equals a maximum count When INT is set to 0 the timer will not issue interrupt requests If the EN enable bit is cleared a...

Page 130: ...are compared to maximum count registers and various actions are triggered based on reaching a maximum count Figure 8 4 Timer Count Registers The value of these registers at reset is undefined Bits 15...

Page 131: ...is method the TMROUT0 or TMROUT1 signals can be used to generate wave forms of various duty cycles Timer 2 has one compare register T2CMPA If a maximum count compare register is set to 0000h the timer...

Page 132: ...Timer Control Unit 8 8...

Page 133: ...1 Six registers in the peripheral control block define the operation of each channel The DMA registers consist of a 20 bit source address 2 registers a 20 bit destination address 2 registers a 16 bit...

Page 134: ...or DMA Control Logic Request Selection Logic Adder Control Logic 20 20 Channel Control Register 1 Channel Control Register 0 16 DRQ1 Serial Port DRQ0 Serial Port Internal Address Data Bus Timer Reques...

Page 135: ...spect to the other DMA channel n Whether timer 2 DMA requests are enabled or disabled n Whether bytes or words are transferred on the Am186 microcontroller only n Whether the DRQ pin is used for exter...

Page 136: ...chronized DMA transfers always terminate when the count reaches 0 regardless of the setting of this bit Bit 8 Interrupt INT When INT is set to 1 the DMA channel generates an interrupt request on compl...

Page 137: ...mportant to note that when a DMA channel is in use by a serial port the corresponding external DMA request signal is deactivated For DMA to the serial port the transmit data register address either I...

Page 138: ...TC bit in the DMA control register However if the TC bit in the DMA control word is set or if unsynchronized transfers are programmed DMA activity terminates when the transfer count register reaches 0...

Page 139: ...performed the address is incremented or decremented by 1 Each register can point into either memory or I O space The user must program the upper four bits to 0000b in order to address the normal 64K I...

Page 140: ...thisregister are combined with the four bits of the DMA Destination Address High register see Figure 9 4 to produce a 20 bit destination address Figure 9 5 DMA Destination Address Low Register The va...

Page 141: ...re performed the address is incremented or decremented by 1 Each register can point into either memory or I O space The user must program the upper four bits to 0000b in order to address the normal 64...

Page 142: ...its of this register are combined with the four bits of the DMA Source Address High register see Figure 9 6 to produce a 20 bit source address Figure 9 7 DMA Source Address Low Register The value of D...

Page 143: ...ive it When destination synchronized transfers are requested the DMA controller relinquishes control of the bus after every transfer If no other bus activity is initiated another DMA cycle begins afte...

Page 144: ...lowed immediately by another DMA transfer 2 This source synchronized transfer is immediately followed by another DMA transfer because DRQ is not deasserted soon enough 9 4 1 2 Destination Synchronizat...

Page 145: ...see Section 9 3 1 bit 5 the P bit DMA cycles always have priority over internal CPU cycles except between locked memory accesses or word accesses to odd memory locations However an external bus hold...

Page 146: ...sfer from occurring between updates to the channel registers 9 4 5 DMA Channels on Reset On reset the state of the DMA channels is as follows n The ST bit for each channel is reset n Any transfer in p...

Page 147: ...parity n One stop bit n Two lengths of break characters n Error detection Parity errors Framing errors Overrun errors n Hardware handshaking with the following selectable control signals Clear to sen...

Page 148: ...be set and the RTS bit should be cleared for the associated serial port To implement the DTE device the ENRX bit should be cleared and the RTS bit should be set for the associated serial port These b...

Page 149: ...have an effect on serial port transmission rates On the Am186ES and Am188ES microcontrollers the RTR signal is not asserted until valid data from a previous transmission has been read out of the recei...

Page 150: ...CT Serial Port 0 Control 82h SP0STS Serial Port 0 Status 88h SP0BAUD Serial Port 0 Baud Rate Divisor 86h SP0RD Serial Port 0 Receive 84h SP0TD Serial Port 0 Transmit 10h SP1CT Serial Port 1 Control 12...

Page 151: ...egister in non DMA mode When the port is configured for DMA transmits the corresponding transmit interrupt is disabled regardless of the setting of the TXIE bit DMA transfers from the serial port func...

Page 152: ...set 2 Set the BRK bit 3 Perform two sequential writes to the transmit register 4 Wait for the TEMT bit in the status register to be set again 5 Write a character with the low nibble zeroed and the hig...

Page 153: ...smit interrupt requests are disabled Bit 5 Receive Mode RMODE When this bit is set the receive section of the serial port is enabled When this bit is reset the receiver is disabled Bit 4 Even Parity E...

Page 154: ...orts are able to exchange data freely It should be noted that only ports which are actively exchanging data i e ports in mode 3 should have hardware handshaking enabled If this is not the case multipl...

Page 155: ...antee detection with the specified 2M 3 bit times the break must begin outside of a frame Note This bit should be reset by software Bit 9 Short Break Detected BRK0 This bit is set when a short break i...

Page 156: ...ad data in the receive register resulting in loss of data Note This bit should be reset by software Bit 3 Parity Error Detected PER This bit is set when the processor detects a parity error modes 1 an...

Page 157: ...EMT and THRE bits in the associated Serial Port Status register When hardware handshaking is enabled the transmitter will not transmit data while RTS RTR inputs are deasserted Data is held in the tran...

Page 158: ...set the receive register contains valid unread data The RDR bit is automatically cleared when the receive register is read When hardware handshaking is enabled the CTS ENRX signals are deasserted whi...

Page 159: ...s in use and interrupts are enabled during power save mode A general formula for the baud rate divisor is BAUDDIV Processor Frequency 16 baud rate The maximum baud rate is 1 16 of the internal process...

Page 160: ...visor Registers The value of SPBAUD at reset is 0000h Bits 15 0 Baud Rate Divisor BAUDDIV This field specifies the divisor for the internal processor clock 128000 9 12 16 19 153600 8 10 13 16 Special...

Page 161: ...resistors or as an open drain output After power on reset the PIO pins default to various configurations The column titled Power On Reset State in Table 11 1 lists the defaults for the PIOs The system...

Page 162: ...Normal operation 3 6 SRDY Normal operation 4 7 1 A17 Normal operation 3 8 1 A18 Normal operation 3 9 1 A19 Normal operation 3 10 TMROUT0 Input with pulldown 11 TMRIN0 Input with pullup 12 DRQ0 INT5 I...

Page 163: ...The value of PIOMODE1 at reset is 0000h Bits15 0 PIO ModeBits PMODE31 PMODE16 Thisfield alongwith thePIOdirection registers determines whether each PIO pin performs its preassigned function or is enab...

Page 164: ...ue of PDIR1 at reset is FFFFh Bits 15 0 PIO Direction Bits PDIR31 PDIR16 This field determines whether each PIO pin acts as an input or an output The most significant bit of the PDIR field determines...

Page 165: ...is configured as an output or an input in the PIO Direction registers The most significant bit of the PDATA field indicates the level of PIO31 the next bit indicates the level of PIO30 and so on The v...

Page 166: ...Programmable I O Pins 11 6...

Page 167: ...se level register F2 AUXCON Auxiliary configuration F0 SYSCON System configuration register E6 WDT Watchdog timer control register E4 EDRAM Enable RCU register E2 CDRAM Clock prescaler register E0 MDR...

Page 168: ...ter 5C T1CMPB Timer 1 maxcount compare B register 5A T1CMPA Timer 1 maxcount compare A register 58 T1CNT Timer 1 count register 56 T0CON Timer 0 mode control register 54 T0CMPB Timer 0 maxcount compar...

Page 169: ...ity mask register Slave master 28 IMASK Interrupt mask register Slave master 26 POLLST Poll status register Master mode 24 POLL Poll register Master mode 22 EOI End of interrupt register Master mode E...

Page 170: ...Hexadecimal FE Reset Configuration Register RESCON Page 4 4 F6 15 7 0 RC Processor Release Level Register PRL Page 4 5 F4 15 7 0 PRL Reserved 15 7 0 Auxiliary Configuration Register AUXCON Page 4 6 EN...

Page 171: ...G NMIFLAG TEST 15 7 0 0 0 0 0 0 T8 T0 0 EN Enable RCU Register EDRAM Page 6 2 E4 15 7 0 0 0 0 0 0 0 RC8 RC0 0 Clock Prescaler Register CDRAM Page 6 2 E2 15 7 0 M6 M0 RA19 RA13 0 Memory Partition Regis...

Page 172: ...s High Register D1DSTH Page 9 7 D6 15 7 0 DDA15 DDA0 DMA 1 Destination Address Low Register D1DSTL Page 9 8 D4 15 7 0 Reserved DSA19 DSA16 DMA 1 Source Address High Register D1SRCH Page 9 9 D2 15 7 0...

Page 173: ...estination Address High Register D0DSTH Page 9 7 C6 15 7 0 DDA15 DDA0 DMA 0 Destination Address Low Register D0DSTL Page 9 8 C4 15 7 0 Reserved DSA19 DSA16 DMA 0 Source Address High Register D0SRCH Pa...

Page 174: ...eral Chip Select Register PACS Page 5 12 A4 R2 15 7 0 R1 R0 0 UB2 UB0 1 1 1 1 DA PSE 1 1 1 A19 Low Memory Chip Select Register LMCS Page 5 6 A2 R2 R2 15 7 0 LB2 LB0 1 0 0 0 0 R7 R1 R0 0 A19 1 1 1 Uppe...

Page 175: ...e 10 9 82 15 7 0 Reserved TEMT THRE RB8 BRK1 OER PER FER BRK0 RDR HS0 RES Serial Port 0 Control Register SP0CT Page 10 5 80 15 7 0 DMA RSIE TXIE BRK RMODE MODE TMODE PE EVN FC RXIE DMA TB8 PIO Data 1...

Page 176: ...ion 0 Register PDIR0 Page 11 4 72 15 7 0 PDIR15 PDIR0 PIO Mode 0 Register PIOMODE0 Page 11 3 70 15 7 0 PMODE15 PMODE0 15 7 0 EN INT INH 0 MC CONT 0 0 0 0 0 0 0 0 0 0 66 Timer 2 Mode Control Register T...

Page 177: ...15 7 0 TC15 TC0 5C Timer 1 Maxcount Compare B Register T1CMPB Page 8 7 15 7 0 TC15 TC0 5A Timer 1 Maxcount Compare A Register T1CMPA Page 8 7 15 7 0 TC15 TC0 58 Timer 1 Count Register T1CNT Page 8 6 1...

Page 178: ...6 MSK Serial Port 0 Interrupt Control Register SP0CON Master Mode Page 7 18 44 15 7 0 Res PR2 Reserved 1 PR1 PR0 42 Serial Port 1 Interrupt Control Register SP1CON Master Mode Page 7 18 15 7 0 MSK Re...

Page 179: ...e Page 7 14 PR2 PR0 MSK 15 7 0 PR2 PR0 Timer 2 Interrupt Control Register T2INTCON 3A Slave Mode Page 7 29 Reserved 15 7 0 Reserved MSK LTM C SFNM INT0 Control Register I0CON 38 Master Mode Page 7 14...

Page 180: ...Register TCUCON Master Mode Page 7 17 Timer 0 Interrupt Control Register T0INTCON Slave Mode Page 7 29 Reserved 15 7 0 Reserved TMR2 TMR0 DHLT Interrupt Status Register INTSTS 30 Master Mode Page 7 1...

Page 181: ...7 0 Reserved D0 D1 TMR1 TMR2 Res TMR0 In Service Register INSERV 2C Slave Mode Page 7 32 2A Master Mode Page 7 23 Slave Mode Page 7 33 15 7 0 Reserved PRM2 PRM0 Priority Mask Register PRIMSK Interrupt...

Page 182: ...25 Reserved 15 7 0 S4 S0 IREQ Poll Register POLL 24 Master Mode Page 7 26 Reserved 15 7 0 S4 S0 NSPEC End of Interrupt Register EOI 22 Master Mode Page 7 27 Reserved 15 7 0 L2 L0 Specific End of Inte...

Page 183: ...Receive Register SP1RD Page 10 12 16 15 7 0 Reserved RDATA Serial Port 1 Transmit Register SP1TD Page 10 11 14 15 7 0 Reserved TDATA Serial Port 1 Status Register SP1STS Page 10 9 12 15 7 0 Reserved T...

Page 184: ...Register Summary A 18...

Page 185: ...SA15 DSA0 DMA Source Address Low 9 10 DSA19 DSA16 DMA Source Address High 9 9 E Enable RCU 6 2 EN Enable Bit 8 3 8 5 EX Pin Selector 5 11 EXT External Clock Bit 8 3 F2 F0 Clock Divisor Select 4 8 FER...

Page 186: ...TMR0 Timer Interrupt Request 7 19 7 30 TMR2 TMR1 Timer 2 Timer 1 Interrupt In Service 7 32 TMR2 TMR1 Timer 2 Timer 1 Interrupt Mask 7 34 TRM2 TMR1 Timer2 Timer1 Interrupt Request 7 31 UB2 UB0 Upper B...

Page 187: ...r 1 Mode Control Register 8 3 External interrupt acknowledge bus cycles table 7 8 F F2 F0 field Clock Divisor Select 4 8 FER bit Framing Error Detected 10 10 Figure external interrupt acknowledge bus...

Page 188: ...sed opcode 7 7 IREQ bit Interrupt Request Poll Register 7 26 Poll Status Register 7 25 IRET interrupt return 7 5 L L2 L0 field Interrupt Type 7 35 LB2 LB0 field Lower Boundary 5 4 Low Memory Chip Sele...

Page 189: ...rupts 7 12 PR2 PR0 field Priority Level DMA Interrupt Control Register 7 29 Timer Interrupt Control Register 7 29 PR2 PR0 field Priority DMA Interrupt Control Registers 7 17 INT0 Control Register 7 14...

Page 190: ...ct MMCS Offset A6h 5 8 PCS and MCS Auxiliary MPCS Offset A8h 5 10 Peripheral Chip Select PACS Offset A4h 5 12 Peripheral Control Block Relocation RELREG Offset FEh 4 3 PIO Data 0 PDATA0 Offset 74h 11...

Page 191: ...mode nesting 7 28 SM IO bit Source Address Space Select 9 4 Software interrupt 7 3 Special fully nested mode 7 12 Specific End of Interrupt Register description Slave mode 7 35 SPI bit Serial Port Int...

Page 192: ...r Interrupt Mask 7 24 TMR bit Timer Interrupt Request 7 21 TMR0 bit Timer 0 Interrupt In Service 7 32 TMR0 bit Timer 0 Interrupt Mask 7 34 TMR0 bit Timer 0 Interrupt Request 7 31 TMR2 TMR0 field Timer...

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