16–24
Chapter 16: Testbench and Design Example
Root Port BFM
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
requests to particular offsets from a BAR. This procedure allows the testbench code
that accesses the Endpoint Application Layer to be written to use offsets from a BAR
and not have to keep track of the specific addresses assigned to the BAR.
shows how those offsets are used.
The configuration routine does not configure any advanced PCI Express capabilities
such as the AER capability.
Table 16–19. BAR Table Structure
Offset (Bytes)
Description
+0
PCI Express address in BAR0
+4
PCI Express address in BAR1
+8
PCI Express address in BAR2
+12
PCI Express address in BAR3
+16
PCI Express address in BAR4
+20
PCI Express address in BAR5
+24
PCI Express address in Expansion ROM BAR
+28
Reserved
+32
BAR0 read back value after being written with all 1’s (used to compute size)
+36
BAR1 read back value after being written with all 1’s
+40
BAR2 read back value after being written with all 1’s
+44
BAR3 read back value after being written with all 1’s
+48
BAR4 read back value after being written with all 1’s
+52
BAR5 read back value after being written with all 1’s
+56
Expansion ROM BAR read back value after being written with all 1’s
+60
Reserved