3–4
Chapter 3: Getting Started with the Avalon-MM Arria V GZ Hard IP for PCI Express
Customizing the Arria V GZ Hard IP for PCI Express IP Core
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
User Guide
For more information about the use of BARs to translate PCI Express addresses to
Avalon-MM addresses, refer to
“PCI Express-to-Avalon-MM Address Translation for
. For more information about minimizing BAR sizes, refer to
“Minimizing BAR Sizes and the PCIe Address Space” on page 5–17
1. For the
Device Identification Registers
, specify the values listed in the center
column of
Table 3–4
. The right-hand column of this table lists the value assigned to
Altera devices. You must use the Altera values to run the Altera testbench. Be sure
to use your company’s values for your final product.
2.
3. Under the
PCI Express and PCI Capabilities
heading, specify the settings in
Table 3–4. Device Identification Registers
Parameter
Value
Altera Value
Vendor ID
0x00000000
0x00001172
Device ID
0x00000001
0x0000E001
Revision ID
0x00000001
0x00000001
Class Code
0x00000000
0x00FF0000
Subsystem Vendor ID
0x00000000
0x00001172
Subsystem Device ID
0x00000000
0x0000E001
Table 3–5. PCI Express and PCI Capabilities
Parameter
Value
Device
Maximum payload size
128 Bytes
Completion timeout range
ABCD
Implement completion timeout disable
Turn on this option
Error Reporting
Advanced error reporting (AER)
Turn off this option
ECRC checking
Turn off this option
ECRC generation
Turn off this option
Link
Link port number
1
Slot clock configuration
Turn on this option
MSI
Number of MSI messages requested
4
MSI-X
Implement MSI-X
Turn this option off
Power Management
Endpoint L0s acceptable latency
Maximum of 64 ns
Endpoint L1 acceptable latency
Maximum of 1 us