6–6
Chapter 6: IP Core Interfaces
Avalon-ST RX Interface
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
rx_st_valid
1, 2
O
valid
Clocks
rx_st_data
into the Application Layer. Deasserts
within 2 clocks of
rx_st_ready
deassertion and reasserts
within 2 clocks of
rx_st_ready
assertion if more data is
available to send.
For 256-bit data, when you turn on
Enable multiple packets
per cycle
, the following correspondences apply:
■
bit 1 applies to
rx_st_data[255:128]
■
bit 0 applies to
rx_st_data[127:0]
rx_st_err
1, 2
O
error
Indicates that there is an uncorrectable error correction coding
(ECC) error in the internal RX buffer. Active when ECC is
enabled. ECC is automatically enabled by the Quartus II
assembler. ECC corrects single-bit errors and detects
double-bit errors on a per byte basis.
When an uncorrectable ECC error is detected,
rx_st_err
is
asserted for at least 1 cycle while
rx_st_valid
is asserted.
For 256-bit data, when you turn on
Enable multiple packets
per cycle
, the following correspondences apply:
■
bit 1 applies to
rx_st_data[255:128]
■
bit 0 applies to
rx_st_data[127:0]
Altera recommends resetting the Arria V GZ Hard IP for PCI
Express when an uncorrectable (double-bit) ECC error is
detected.
Component Specific Signals
rx_st_mask
1
I
component
specific
The Application Layer asserts this signal to tell the Hard IP to
stop sending non-posted requests. This signal can be asserted
at any time. The total number of non-posted requests that can
be transferred to the Application Layer after
rx_st_mask
is
asserted is not more than 10.
rx_st_bardec1
rx_st_bardec2
8
O
component
specific
The decoded BAR bits for the TLP. Valid for
MRd
,
MWr
,
IOWR
, and
IORD
TLPs; ignored for the completion or message TLPs.
rx_st_bardec1
is valid on the first cycle of
rx_st_data
for
TLPs that begin in the lower 2 qwords of
rx_st_data
([127:0]). When using a 256-bit Avalon-ST bus
with
Multiple packets per cycle
,
rx_st_bardec2
is valid on
the first cycle of
rx_st_data
for TLPs that begin in the upper 2
qwords of
rx_st_data
([255:128]).
and
illustrate the timing of this signal for 64- and 128-bit data,
respectively.
Table 6–3. 64-, 128-, or 256-Bit Avalon-ST RX Datapath (Part 3 of 4)
Signal
Width
Dir
Avalon-ST
Type
Description