2–12
Chapter 2: Getting Started with the Arria V GZ Hard IP for PCI Express
Qsys Design Flow
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
User Guide
Simulating the Example Design
Follow these steps to compile the testbench for simulation and run the chaining DMA
testbench.
1. Start your simulation tool. This example uses the ModelSim
®
software.
2. From the ModelSim transcript window, in the testbench directory
(.
/example_design/altera_pcie_
<device>
_hip_ast/
<variant>
/testbench/mentor
)
type the following commands:
a.
source msim_setup.tcl
r
b. h
r
(This is the ModelSim help command.)
c. ld_debug
r
(This command compiles all design files and elaborates the
top-level design without any optimization.)
d. run -all
r
shows a partial transcript from a successful simulation. As this transcript
illustrates, the simulation includes the following stages:
■
Link training
■
Configuration
■
DMA reads and writes
■
Root Port to Endpoint memory reads and writes
<testbench_dir>/<variant_name>/
testbench/
Includes testbench subdirectories for the Aldec, Cadence and Mentor simulation
tools with the required libraries and simulation scripts.
<testbench_dir>/<variant_name>/
testbench/
<cad_vendor>
Includes the HDL source files and scripts for the simulation testbench.
Table 2–10. Qsys Generation Output Files (Part 2 of 2)
Directory
Description
Example 2–1. Excerpts from Transcript of Successful Simulation Run
Time: 56000 Instance: top_chaining_testbench.ep.epmap.pll_250mhz_to_500mhz.
# Time: 0 Instance:
pcie_de_gen1_x8_ast128_tb.dut_pcie_tb.genblk1.genblk1.altpcietb_bfm_top_rp.rp.rp.nl00O
0i.Arria V GZii_pll.pll1
# Note : Arria V GZ II PLL locked to incoming clock
# Time: 25000000 Instance:
pcie_de_gen1_x8_ast128_tb.dut_pcie_tb.genblk1.genblk1.altpcietb_bfm_top_rp.rp.rp.nl00O
0i.Arria V GZii_pll.pll1
# INFO: 464 ns Completed initial configuration of Root Port.
# INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 3693 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 3905 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 4065 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 6369 ns EP LTSSM State: POLLING.CONFIG
# INFO: 6461 ns RP LTSSM State: POLLING.CONFIG
# INFO: 7741 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 7969 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 8353 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 8781 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT