6–42
Chapter 6: IP Core Interfaces
Parity Signals
Arria V GZ Hard IP for PCI Express
November 2012
Altera Corporation
Parity Signals
You enable parity checking by selecting
Enable byte parity ports on the Avalon-ST
interface
under the
System Settings
heading of the parameter editor. Parity is odd.
This option is not available for the Avalon-MM Arria V GZ Hard IP for PCI Express.
Parity protection provides some data protection in systems that do not use ECRC
checking.
On the RX datapath, parity is computed on the incoming TLP prior to the LCRC check
in the Data Link Layer. Up to 32 parity bits are propagated to the Application Layer
along with the RX Avalon-ST data. The RX datapath also propagates up to 32 parity
bits to the Transaction Layer for Configuration TLPs. On the TX datapath, parity
generated in the Application Layer is checked in Transaction Layer and the Data Link
Layer.
[3:1]
multiple
message
capable
Multiple message capable: This field is read by system software to determine the
number of requested MSI messages.
■
3’b000: 1 MSI requested
■
3’b001: 2 MSI requested
■
3’b010: 4 MSI requested
■
3’b011: 8 MSI requested
■
3’b100: 16 MSI requested
■
3’b101: 32 MSI requested
■
3’b110: Reserved
[0]
MSI Enable
If set to 0, this component is not permitted to use MSI.
Table 6–18. Configuration MSI Control Status Register Field Descriptions (Part 2 of 2)
Bit(s)
Field
Description