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Description of the data path
STINGRAY Technical Manual
V4.4.2
146
Flow diagram of defect pixel correction
The following flow diagram illustrates the defect pixel detection:
Figure 69: Defect pixel correction: build and store
Note
While building defect pixel correction data or uploading
them from host, the defect pixel correction data are
stored volatile in FPGA.
Optional you can store the data in a non-volatile memory
(Set MemSave to 1).
Note
Configuration
To configure this feature in an advanced register: See
143: Advanced register: Defect pixel correction
Set resolution to
Format_7 Mode_x
Or
Set resolution to
Format_7 Mode_0
when using fixed
modes.
Set AOI to max.
Choose threshold
Set
BuildDPData
to 1
Set
ON_OFF
to 1
Optional:
Set
MemSave
to 1
Set values for
shutter, gain
to max.