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ACE1553-3U-4 Hardware Manual
11
Figure 3.3: GPIO Protection with external resistor
Global RAM
3.2
The Global RAM is shared between both BIU processors (BIP) and the Host PCIe-Bus. The
arbitration is handled by the common FPGA. It has access to the common Global RAM via a 32
bit wide data port.
BIU Section
3.3
Up to two Bus Interface Units (BIUs) are implemented on the ACE1553-3U module. Both BIUs
implement exactly the same functionality. Each BIU handle up to two MIL-STD-1553B channels
and provide the trigger signals for BC, RT and BM applications. The control logic is
implemented in the common FPGA device.
Discrete IO-Pin
Front Connector
Off-Board User Voltage
Customized
Discrete Output
R
serial
ACE1553-3U-x Board
GND
FPGA
Output
Pin
Summary of Contents for ACE1553-3U-4
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