Aim ACE1553-3U-4, Hardware Manual

Page: 9 / 35

ACE1553-3U-4 Hardware Manual 1
1 INTRODUCTION
General 1.1
This document comprises the Hardware User’s Manual for the ACE1553-3U-4 PXIe-Module.
The document covers the hardware installation, the board connections the technical data and a
general description of the hardware architecture. For programming information please refer to
the documents listed in the “Applicable Documents” section.
The ACE1553 modules are members of AIM's new family of advanced PXI-Express cards
compliant to PCI Express V1.1 communication standard. The PCI-Express Interface is 1-lane
wide and works with 2.5 Gbit/s in transmit and receive direction.
The ACE1553 modules are used to simulate, monitor and inject protocol errors of MIL-STD-
1553A/B based databus systems. The ACE1553-3U-4 offers an interface for up to four dual-
redundant MIL-STD-1553 bus channels. Furthermore the interface implements trigger IN/OUT
functions for Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM), as well as 2
user programmable Discrete I/O signals.
Additionally, a free-wheeling IRIG-B time code generator allows the user to synchronize to
either the onboard generated time code or the time code of an external board with a resolution
of 1us.
Transformer-, Direct-, Network Emulation- and Isolated Coupling- Modes are available at the
external interface connector. A standard breakout cable (2.0 m) is available for the ACE1553
card from HD-DSUB15 connector to four (two, if ACE1553-3U-1 module) PL-75 Twinax
Connectors.
The hardware architecture provides enough resources (i.e. processing capability and memory)
to guarantee, that all specified interface functions are available concurrently and to full
performance specifications.
A powerful PCI-Express Controller and Memory Arbiter are implemented in a Field
Programmable Gate Array (FPGA). This FPGA supports both, the interface to the application
and driver software tasks running on the host computer and assists the communication for data
transfer.
This feature expands the capability of the ACE1553 module to that of a high level instrument.
To fulfil the real-time requirements of a typical avionic type databus system, a high performance
32bit RISC processor (BIP) is implemented for each Bus Interface Unit (BIU) / each MIL-STD-
1553A/B stream.
A free-wheeling IRIG-B Time code Encoder/Decoder is implemented on the ACE1553 to satisfy
the requirements of “multi-channel time tag synchronization” on the system level. The IRIG-B
compatible amplitude modulated sinewave output allows the synchronization of any external
module implementing IRIG-B time stamping.
The module can be installed in standard cPCIe (3U) peripheral/hybrid slots and PXIe
peripheral/hybrid slots. If installed in a PXIe slot, 8 PXI Trigger I/O and a PXI System Reference
Clock (10MHz) based time tag mode are supported.