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ACE1553-3U-4 Hardware Manual
8
PCI-Express Interface and BIU-I/O FPGA
3.1
The new common FPGA architecture of AIM’s PCI-Express family includes both the complete
PCI-Express bus logic and the BIU processor logic. This programmable device implements the
following features:
PCI Express 1.1 compliant bus interface
Global RAM interface and arbitration
Boot function
SPI controller for update programming
MIL-STD-1553 Encoder
MIL-STD-1553 Decoder
IRIG Encoder and decoder support
System & Maintenance Controller / RS232 Maintenance Interface
External Trigger Inputs and Outputs
User programmable GPI/Os
PXI Instrumentation Bus Capabilities
3.1.1 Global RAM Interface and Arbitration
The Global RAM Arbiter and the Global RAM interface port are implemented in the FPGA. The
Arbiter controls Global RAM access between the participants (BIU Processors, PCIe, and the
Timecode Processor) in a fair arbitration scheme
3.1.2 Boot Function
To provide maximum flexibility and upgradeability, the FPGA device and the processor are
booted automatically after power up.
3.1.3 Controller for SPI-Flash update programming
IP-Core SPI-Controller to program the on board SPI-Flash memory.
3.1.4 MIL-STD-1553 Encoder
The MIL-STD-1553 encoder comprises a Manchester Encoder with full error injection capability.
The encoder is used to generate faulty (or fault free) command and data words on the bus. This
encoder allows the user to insert protocol errors as required by the 'Remote Terminal
Production Test Plan'.
3.1.5 MIL-STD-1553 Decoder
The MIL-STD-1553 decoder comprises a Manchester Bi-phase decoding unit which samples
the incoming serial data stream. The decoder detects the synchronization pattern
(Command/Status and Data Sync.), converts 16 bit Manchester encoded serial data to parallel
Summary of Contents for ACE1553-3U-4
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