Abov MC97F6108A, User Manual, Page: 56 / 256

6. Interrupt controller MC97F6108A User’s manual
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6.11 Interrupt timing
NOTE : Variable x and n of a command cycle CnPn imply the followings:
 L ➔ Last cycle, 1 ➔ 1 st cycle, 1 st phase, 2 ➔ 2 nd cycle, 2 nd phase
Figure 22. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction
Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the
lower 8-bit of interrupt vector (INT_VEC) is decided. M8051EW core makes interrupt acknowledge at
the first cycle of a command, and executes long call to jump to interrupt service routine.
CLP2 CLP1 C2P1 C1P1 C2P2 C1P2 CLP2
Interrupt sampled here
8-bit interrupt Vector
INT_SRC
INTR_ACK
LAST_CYC
INTR_LCALL
INT_VEC
PROGA
SCLK