11. PPG (Programmable Pulse Generator)
MC97F6108A User’s manual
106
11.8.3
PPG period when ATPSEL = 2'b01
When comparator 2 outputs low and ATPSEL is 2'b01, ATPHR/ATPLR (the period register in auto
period mode) is PPGPH/PPGPL.
{PPGH, PPGL}
(16-bit Counter)
ATPRL
(8-bit)
0 1
MUX
- DSTEP[7:0]
00 01 10 11
MUX
CPOUT2
(in the previous period)
current period
+ USTEP[7:0]
increase
decrease
ATPSEL[1:0]
ATPEN
0 1
MUX
PPGPL
(8-bit)
PPG start
read only
PPG period register
PERIOD write
M 0
U
X 1
M 0
U
X 1
ATPMAXHR
(8-bit)
ATP_MAX
ATPEN
~(PERIOD write)
M
A
X
m
a
tc
h
M
IN
m
a
tc
h
current period
current period
ATPEN
PPGPH
(8-bit)
ATPMAXHR
(8-bit)
ATPMINHR
(8-bit)
ATPMINHR
(8-bit)
ATPRH
(8-bit)
period matching
CMP2
C2DBSEL[1:0
]
by pass
0.3 us
0.6 us
1.2 us
ATP_MIN
Figure 47. Auto Period Mode Block Diagram (ATPSEL = 2'b01)
PPGO
ATPHR, ATPLR
start pulse
1
A
CPOUT2
DSTEP
9
PPGPH/PPGPL
A
9
9
PERIOD=A
PERIOD=9
PERIOD=8
PERIOD=A
PERIOD=9
PERIOD=A
PERIOD=9
< ATPSEL = 2'b01 >
8
A
A
ATPEN
Figure 48. Auto Period Mode (ATPSEL = 2'b01)