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MC97F60128
ABOV Semiconductor Co., Ltd.
9. I/O Ports
9.1
I/O Ports
The MC97F60128 has thirteen groups of I/O ports (P0 ~ PB/PD). Each port can be easily configured by software as
I/O pin, internal pull-up and open-drain pin to meet various system configurations and design requirements. Also
P0 ,P1, P4, P6, P9 and PA includes function that can generate interrupt according to change of state of the pin.
9.2
Port Register
9.2.1
Data Register (Px)
Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to the
corresponding bit of the Px. If ports are configured as input ports, the data can be read from the corresponding bit of
the Px.
9.2.2
Direction Register (PxIO)
Each I/O pin can be independently used as an input or an output through the PxIO register. Bits cleared in this register
will make the corresponding pin ofPx to input mode. Set bits of this register will make the pin to output mode. Almost
bits are cleared by a system reset, but some bits are set by a system reset.
9.2.3
Pull-up Resistor Selection Register (PxPU)
The on-chip pull-up resistor can be connected to I/O ports individually with a pull-up resistor selection register (PxPU).
The pull-up register selection controls the pull-up resister enable/disable of each port. When the corresponding bit is 1,
the pull-up resister of the pin is enabled. When 0, the pull-up resister is disabled. All bits are cleared by a system reset.
9.2.4
Open-drain Selection Register (PxOD)
There are internally open-drain selection registers (PxOD) for P0 ~ PB and a bit for PD. The open-drain selection
register controls the open-drain enable/disable of each port. Almost ports become push-pull by a system reset, but
some ports become open-drain by a system reset.
9.2.5
Debounce Enable Register (PxDB)
P0[7:1], P1[5:0], P4[5:3], P6[2:1], P9[4:0] and PA[4:0] support debounce function. Debounce clocks of each ports are
fx/1, fx/4, fx/4096 and f
SUB
.
Summary of Contents for MC97F60128
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