278
MC97F60128
ABOV Semiconductor Co., Ltd.
USInDR (USI0/1 Data Register: For UART, SPI and I2C mode) : 403CH/404CH (XSFR), n = 0 and 1
7
6
5
4
3
2
1
0
USInDR7
USInDR6
USInDR5
USInDR4
USInDR3
USInDR2
USInDR1
USInDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
USInDR[7:0]
The USIn transmit buffer and receive buffer share the same I/O address with this
DATA register. The transmit data buffer is the destination for data written to the
USInDR register. Reading the USInDR register returns the contents of the receive
buffer.
Write to this register only when the DREn flag is set. In SPI master mode, the SCK
clock is generated when data are written to this register.
USInSDHR (USI0/1 SDA Hold Time Register: For I2C mode) : 403BH/404BH (XSFR), n = 0 and 1
7
6
5
4
3
2
1
0
USInSDHR7
USInSDHR6
USInSDHR5
USInSDHR4
USInSDHR3
USInSDHR2
USInSDHR1
USInSDHR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 01H
USInSDHR[7:0]
The register is used to control SDAn output timing from the falling edge of SCLn in
I2C mode.
NOTE)
1.
That SDA is changed after t
SCLK
X USInSDHR. In master
mode, load half the value of USInSCLR to this register to
make SDA change in the middle of SCL.
2.
In slave mode, configure this register regarding the
frequency of SCL from master.
3.
The SDA is changed after t
SCLK
X (U2) in master
mode. So, to insure operation in slave mode, the value
t
SCLK
X (US 1) must be smaller than the period of
SCL.
USInSCHR (USI0/1 SCL High Period Register: For I2C mode) : 403EH/404EH (XSFR), n = 0 and 1
7
6
5
4
3
2
1
0
USInSCHR7
USInSCHR6
USInSCHR5
USInSCHR4
USInSCHR3
USInSCHR2
USInSCHR1
USInSCHR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 3FH
USInSCHR[7:0]
This register defines the high period of SCLn when it operates in I2C master mode.
The base clock is SCLK, the system clock and the period is calculated by the
formula: t
SCLK
X (4 X US 2) where t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
f
I2C
=
t
SCLK
X (4 X (US USInSCHR) + 4)
1
Summary of Contents for MC97F60128
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Page 18: ...18 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 2 80 Pin LQFP 1212 Package...
Page 19: ...19 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 3 80 Pin LQFP 1414 Package...
Page 20: ...20 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 4 64 Pin LQFP 1414 Package...