238
MC97F60128
ABOV Semiconductor Co., Ltd.
11.12.3 Clock Generation
Figure 11.57
Clock Generation Block Diagram (where n = 2,3 and 4)
The clock generation logic generates the base clock for the transmitter and receiver.
Following table shows equations for calculating the baud rate (in bps).
Operating Mode
Equation for Calculating Baud Rate
Normal Mode(U2Xn=0)
Baud Rate =
fx
16(U 1)
Double Speed Mode(U2Xn=1)
Baud Rate =
fx
8(U 1)
Table 11-19
Equations for Calculating Baud Rate Register Setting(where n = 2,3 and 4)
Baud Rate
Generator
UARTnBD
/2
/8
SCLK
f
SCLK
(1
)
rxclk
M
U
X
U2Xn
txclk
Summary of Contents for MC97F60128
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