Abov MC97F60128, User Manual, Page: 277 / 382

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MC97F60128 ABOV Semiconductor Co., Ltd.
11.13.35 Register Map
Name Address Dir Default Description
USInCR1 4030H/4040H (XSFR) R/W 00H USIn Control Register 1
USInCR2 4031H/4041H (XSFR) R/W 00H USIn Control Register 2
USInCR3 4032H/4042H (XSFR) R/W 00H USIn Control Register 3
USInCR4 4033H/4043H (XSFR) R/W 00H USIn Control Register 4
USInST1 4038H/4048H (XSFR) R/W 00H USIn Status Register 1
USInST2 4039H/4049H (XSFR) R 00H USIn Status Register 2
USInBD 403AH/404AH (XSFR) R/W FFH USIn Baud Rate Generation Register
USInSDHR 403BH/404BH (XSFR) R/W 01H USIn SDA Hold Time Register
USInDR 403CH/404CH (XSFR) R/W 00H USIn Data Register
USInSCLR 403DH/404DH (XSFR) R/W 3FH USIn SCL Low Period Register
USInSCHR 403EH/404EH (XSFR) R/W 3FH USIn SCL High Period Register
USInSAR 403FH/404FH (XSFR) R/W 00H USIn Slave Address Register
Table 11-24 USI0/1 Register Map (where n = 0 and 1)
11.13.36 Register Description
USI0/1 module consists of USI0/1 baud rate generation register (USInBD), USI0/1 data register (USInDR), USI0/1
SDA hold time register (USInSDHR), USI0/1 SCL high period register (USInSCHR), USI0/1 SCL low period Register
(USInSCLR), USI0/1 slave address register (USInSAR), USI0/1 control register 1/2/3/4 (USInCR1/2/3/4), USI0/1
status register 1/2 (USInST1/2).
11.13.37 Register Description for USI0/1
USInBD (USI0/1 Baud- Rate Generation Register: For UART and SPI mode) : 403AH/404AH (XSFR),
n = 0 and 1
7 6 5 4 3 2 1 0
USInBD7 USInBD6 USInBD5 USInBD4 USInBD3 USInBD2 USInBD1 USInBD0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value : FFH
USInBD[7:0] The value in this register is used to generate internal baud rate in asynchronous
mode or to generate SCKn clock in SPI mode. To prevent malfunction, do not write
‘0’
in asynchronous mode and do not write
‘0’ or ‘1’ in SPI mode.
NOTE)
1.
In common with USInSAR register, USInBD register is
used for slave address register when the USI0/1 I2C mode.