manualshive.com logo in svg

Abov MC97F60128, User Manual, Page: 341 / 382

Share
Download
Abov MC97F60128 User Manual Download Page 341

 

341

 

MC97F60128 

ABOV Semiconductor Co., Ltd. 

 

 

 

 

 

Figure 13.6 

Boot Process WaveForm 

 

Process 

Description 

Remarks 

①

 

-No Operation 

 

②

 

-1st POR level Detection 

-about 1.4V 

③

 

-(INT-OSC 8MHz/8)x256x28h Delay section (=10ms) 
-VDD  input  voltage  must  rise  over  than  flash 
operating voltage for Config read 

-Slew Rate 

>=

  0.05V/ms 

④

 

- Config read point 

-about 1.5V ~ 1.6V 
-Config  Value  is  determined  by 
Writing Option 

⑤

 

- Rising section to Reset Release Level 

-16ms  point  after  POR  or 
Ext_reset release 

⑥

 

- Reset Release section (BIT overflow) 
i)  after16ms,  after  External  Reset Release  (External 
reset) 
ii) 16ms point after POR (POR only) 

-  BIT  is  used  for  Peripheral 
stability 

⑦

 

-Normal operation 

 

 

Table 13-2 

Boot Process Description 

 
 

 

Reset Release

 

Config Read

 

POR

 

:VDD Input

 

:Internal OSC

 

①

 

②

 

③

 

④

 

⑤

 

⑥

 

⑦

 

Summary of Contents for MC97F60128

Page 1: ...ator 5 kHz Peripheral features 12 bit Analog to Digital Converter 15 inputs 12 bit Digital to Analog Converter 1 output Fine ADPCM decoder 32kbps fs 8 kHz UART 8 bit x 3 ch SPI 8 bit x 2 ch USI 8 bit...

Page 2: ...5 06 26 Fix the typo Change a Device Name MC97F66128L14 to MC97F67128LB14 Change a Device Name MC97F66128AL14 to MC97F66128LB14 1 2 2015 10 15 Remove invalid contents about LCD bias Modify invalid con...

Page 3: ...miconductor offices in Korea or distributors ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this...

Page 4: ...uzzer driving port SPI UART I2C USI 12 bit A D converter 12 bit D A converter FADPCM on chip POR LVR LVI on chip oscillator and clock circuitry The MC97F60128 also supports power saving modes to reduc...

Page 5: ...llator 8 Bit 3ch T0 T1 T2 16 Bit 4ch T3 T4 T5 T6 8 Bit 2ch T7 T8 or 16 Bit 1ch T7 Programmable Pulse Generation 8 Bit PWM by T0 T1 T2 Pulse generation by T3 T4 T5 T6 6 ch 10 Bit PWM for Motor by T8 Wa...

Page 6: ...TA 0 50 C Power Down Mode STOP IDLE mode Operating Voltage and Frequency 1 8V 5 5V 32 38kHz with X tal 2 0V 5 5V 0 4 4 2MHz with X tal Crystal 1 8V 5 5V 0 4 4 2MHz with X tal Ceramic 2 7V 5 5V 0 4 12...

Page 7: ...system The OCD2 can read or change the value of MCU internal memory and I O peripherals And the OCD2 also controls MCU internal debugging logic it means OCD2 controls emulation step run monitoring etc...

Page 8: ...8 MC97F60128 ABOV Semiconductor Co Ltd 1 3 3 Programmer Single programmer E PGM It programs MCU device directly DSDA VDD DSCL VSS RUNFLAG Figure 1 3 E PGM Single writer...

Page 9: ...ports ISP In System Programming It does not require additional H W except developer s target system Gang programmer E GANG4 and E GANG6 It can run PC controlled mode It can run standalone without PC c...

Page 10: ...five signal lines including VDD and VSS pins for programming FLASH with serial protocol Therefore the on board programming is possible if the programming signal lines are considered when the PCB of ap...

Page 11: ...tion NOTE 1 In on board programming mode very high speed signal will be provided to pin DSCL and DSDA And it will cause some damages to the application circuits connected to DSCL or DSDA port if the a...

Page 12: ...1 channel 8 bit UART 5 channels 8 bit SPI 4 channels 8 bit I2C 2 channels 8 bit CORE M8051 General purpose I O 20 ports normal I O 68 ports LCD shared I O Watchdog timer 8 channels 8 bit 32kHz interna...

Page 13: ...P50 SEG18 RXD4 P41 SEG30 EC1 P46 SEG35 BUZO P45 SEG34 EINT12 T2O PWM2O P42 SEG31 EC2 P44 SEG33 EINT11 T1O PWM1O P43 SEG32 EINT10 T0O PWM0O P31 SEG38 TXD0 SDA0 MOSI0 P30 SEG37 SCK0 P47 SEG36 SS0 P11 S...

Page 14: ...ACB3 P22 SEG47 SS3 CSB3 P21 SEG46 SCK3 P34 SEG41 MOSI2 P33 SEG40 MISO2 LDACB2 P32 SEG39 RXD0 SCL0 MISO0 P87 SEG17 P86 SEG16 P40 SEG29 EC0 P52 SEG20 RXD3 P51 SEG19 TXD4 P54 SEG22 SS1 P53 SEG21 TXD3 P56...

Page 15: ...I2 P33 SEG40 MISO2 LDACB2 P32 SEG39 RXD0 SCL0 MISO0 P40 SEG29 EC0 P52 SEG20 RXD3 P54 SEG22 SS1 P53 SEG21 TXD3 P56 SEG24 TXD1 SDA1 MOSI1 P55 SEG23 SCK1 P41 SEG30 EC1 P46 SEG35 BUZO P45 SEG34 EINT12 T2O...

Page 16: ...0 MISO2 LDACB2 P32 SEG39 RXD0 SCL0 MISO0 P40 SEG29 EC0 P52 SEG20 RXD3 P54 SEG22 SS1 P53 SEG21 TXD3 P56 SEG24 TXD1 SDA1 MOSI1 P55 SEG23 SCK1 P41 SEG30 EC1 P46 SEG35 BUZO P45 SEG34 EINT12 T2O PWM2O P42...

Page 17: ...17 MC97F60128 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 100 pin LQFP 1414 Package...

Page 18: ...18 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 2 80 Pin LQFP 1212 Package...

Page 19: ...19 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 3 80 Pin LQFP 1414 Package...

Page 20: ...20 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 4 64 Pin LQFP 1414 Package...

Page 21: ...as a schmitt trigger input a push pull output or an open drain output A pull up resistor can be specified in 1 bit unit The P20 P23 are not in the 64 Pin package Input SEG45 MOSI3 P21 SEG46 SCK3 P22 S...

Page 22: ...A P73 SEG4 VLC0 PWM8CB P74 COM3 P75 COM2 P76 COM1 P77 COM0 P80 I O Port 8 is a bit programmable I O port which can be configured as an input a push pull output or an open drain output A pull up resist...

Page 23: ...C6 DSDA EINTA P90 AN12 EINTB P91 AN13 EINTC P92 AN14 EINTD P93 EINTE P94 EINTF PA0 SEG53 EINTG PA1 SEG54 EINTH PA2 SEG55 EINTI PA3 SEG56 EINTJ PA4 SEG57 EINT10 I O External interrupt input and Timer 0...

Page 24: ...8 T8O PWM8AB P60 SEG0 PWM8BA P70 SEG1 VLC3 PWM8BB P71 SEG2 VLC2 PWM8CA P72 SEG3 VLC1 PWM8CB P73 SEG4 VLC0 BLNK I O External Sync Signal Input for 6 ch PWMs Input P00 AN0 EINT0 EC0 EC2 I O Timer 0 1 2...

Page 25: ...UART 1 data input Input P57 SEG25 SCL1 MISO1 RXD2 I O UART 2 data input Input P65 AN11 RXD3 I O UART 3 data input Input P52 SEG20 RXD4 I O UART 4 data input Input P50 SEG18 SCL0 I O I2C 0 clock input...

Page 26: ...EXTSP1 SEG0 I O LCD segment signal outputs Input P60 SEG0 PWM8AB SEG1 P70 VLC3 PWM8BA SEG2 P71 VLC2 PWM8BB SEG3 P72VLC1 PWM8CA SEG4 P73 VLC0 PWM8CB SEG5 PD0 SEG6 PD1 SEG7 PD2 SEG8 PD3 SEG9 PD4 SEG10 P...

Page 27: ...53 PA0 EINTF SEG54 PA1 EINTG SEG55 PA2 EINTH SEG56 PA3 EINTI SEG57 PA4 EINTJ SEG58 P10 EINT13 T3O PWM3O EXTSP2 SEG59 P11 EINT14 T4O PWM4O SEG60 P12 EINT15 T5O PWM5O SEG61 P13 EINT16 T6O PWM6O SEG62 P1...

Page 28: ...he VREG are not in the 64 Pin MC97F66128LB14 package AVREF A D converter reference voltage AVSS Analog power input pins The AVSS are not in the 64 Pin MC97F66128LB14 package VDD1 VSS1 VDD2 VSS2 Digita...

Page 29: ...VDD OPEN DRAIN REGISTER DATA REGISTER DIRECTION REGISTER MUX 0 1 MUX 1 0 CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or SUB FUNC DATA INPUT SUB FUNC DIRECTION SUB FUNC E...

Page 30: ...1 0 INTERRUPT ENABLE EXTERNAL INTERRUPT Q D CP r VDD FLAG CLEAR POLARITY REG MUX 1 0 DEBOUNCE ENABLE Q D CP r DEBOUNCE CLK CMOS or Schmitt Level Input ANALOG CHANNEL ENABLE ANALOG INPUT PORTx INPUT or...

Page 31: ...d under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the oper...

Page 32: ...2 mA Disable 0 1 uA Table 7 3 A D Converter Characteristics NOTE 1 Zero offset error is the difference between 000000000000 and the converted output for zero input voltage AVSS 2 Top offset error is...

Page 33: ...35 2 17 2 32 2 47 2 29 2 44 2 59 2 39 2 59 2 79 2 55 2 75 2 95 2 73 2 93 3 13 2 94 3 14 3 34 3 18 3 38 3 58 3 37 3 67 3 97 3 70 4 00 4 30 4 10 4 40 4 70 Hysteresis V 50 150 mV Minimum Pulse Width tLW...

Page 34: ...Ratio TOD 40 50 60 Stabilization Time THFS 100 us IRC Current IIRC Enable 0 2 mA Disable 0 1 uA Table 7 8 Internal RC Oscillator Characteristics NOTE 1 A 0 1uF bypass capacitor should be connected to...

Page 35: ...CR 0AH VDDx16 21 LCDCCR 0BH VDDx16 20 LCDCCR 0CH VDDx16 19 LCDCCR 0DH VDDx16 18 LCDCCR 0EH VDDx16 17 LCDCCR 0FH VDDx16 16 LCD Mid Bias Voltage note VLC1 VDD 2 7V to 5 5V LCD clock 0Hz 1 4 bias No pane...

Page 36: ...RPU2 VI 0V TA 25 C RESETB VDD 5 0V 150 250 400 k VDD 3 0V 300 500 700 Pull Down Resistor RPD VDD 5 0V TA 25 C RUNFLAG 10 20 30 k OSC feedback resistor RX1 XIN VDD XOUT VSS TA 25 C VDD 5V 600 1200 200...

Page 37: ...conductor Co Ltd 2 All supply current items don t include the current of an internal watch dog timer RC WDTRC oscillator and a peripheral block 3 All supply current items include the current of the po...

Page 38: ...nterrupt input high low width tIWH tIWL All interrupt VDD 5V 200 ns External Counter Input High Low Pulse Width tECWH tECWL ECn VDD 5V n 0 1 2 3 4 5 6 7 200 External Counter Transition Time tREC tFEC...

Page 39: ...Internal SCK source 70 Input Clock High Low Pulse Width External SCK source 70 First Output Clock Delay Time tFOD Internal External SCK source 100 Output Clock Delay Time tDS 50 Input Setup Time tDIS...

Page 40: ...ta valid tS2 590 ns Output data hold after clock rising edge tH1 tCPU 50 tCPU ns Input data hold after clock rising edge tH2 0 ns Serial port clock High Low level width tHIGH tLOW 470 tCPU x 8 970 ns...

Page 41: ...th tSCLL 4 7 1 3 Bus Free Time tBF 4 7 1 3 Start Condition Setup Time tSTSU 4 7 0 6 Start Condition Hold Time tSTHD 4 0 0 6 Stop Condition Setup Time tSPSU 4 0 0 6 Stop Condition Hold Time tSPHD 4 0 0...

Page 42: ...mer Active VDD NOTE tWAIT is the same as the selected bit overflow of BIT X 1 BIT Clock INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode 0 8VDD tWAIT VDDDR Figu...

Page 43: ...g Frequency fPGM 0 4 MHz Endurance of Write Erase NFWE 10 000 times Flash Data Retention Time tRT 10 years Table 7 18 Internal Flash Rom Characteristics NOTE During a flash operation SCLK 1 0 of SCCR...

Page 44: ...on frequency 2 0V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 12 0 Ceramic Oscillator Main oscillation frequency 1 8V 5 5V 0 4 4 2 MHz 2 7V 5 5V 0 4 12 0 External Clock XIN input frequency 1 8V 5 5V 0 4 4 2 MHz 2...

Page 45: ...r Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 1 8V 5 5V 32 32 768 38 kHz External Clock SXIN input frequency 32 100 kHz Table 7 21 Sub Clock Oscillator Characteristics SXIN...

Page 46: ...o the minimum oscillator voltage range 10 ms External Clock fXIN 0 4 to 10MHz XIN input high and low width tXH tXL 42 1250 ns Table 7 22 Main Oscillation Stabilization Characteristics tXH tXL XIN 0 2V...

Page 47: ...5 12 0MHz fXIN 0 4 to 10MHz Supply voltage for Ceramic V 4 2MHz 2 0 0 4MHz 2 7 5 5 12 0MHz fXIN 0 4 to 10MHz Supply voltage for Crystal V 4 2MHz Figure 7 14 Operating Voltage Range MAIN OSC 1 8 5 5 32...

Page 48: ...tput of an internal regulator for sub oscillator So this 0 1uF capacitor is needed and should be as close by the MCU as possible if the sub clock is used for system 0 1uF VDD VCC The MCU power line VD...

Page 49: ...e The R1 and C2 should be as close by the C3 as possible The R1 is optional so it may not apply 3 The C3 capacitor is used for temperature compensation because an electrolytic capacitor becomes worse...

Page 50: ...e data presented in this section is a statistical summary of data collected on units from different lots over a period of time Typical represents the mean of the distribution while max or min represen...

Page 51: ...d Figure 7 20 SUB RUN IDD3 Current Figure 7 21 SUB IDLE IDD4 Current 0 0 20 0 40 0 60 0 80 0 100 0 120 0 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V uA 40 25 85 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 2 5V 3 0...

Page 52: ...52 MC97F60128 ABOV Semiconductor Co Ltd Figure 7 22 STOP IDD5 Current 0 00 0 50 1 00 1 50 2 00 2 50 3 00 3 50 4 00 4 50 2 5V 3 0V 3 5V 4 0V 4 5V 5 0V 5 5V uA 40 25 85...

Page 53: ...pable of addressing up to 64 Kbytes for one bank of memory space but this device has 128K bytes program memory space with bank selection scheme Figure 8 1 shows the map of the lower part of the progra...

Page 54: ...54 MC97F60128 ABOV Semiconductor Co Ltd FFFFH 64K Bytes Bank 1 FFFFH 0000H 64K Bytes Bank 0 Total 128k Bytes Figure 8 1 Program Memory NOTE 128 Kbytes Including Interrupt Vector Region...

Page 55: ...cess a different memory space Thus Figure 8 2 shows the upper 128 bytes and SFR space occupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128...

Page 56: ...bytes 07H 00H 8 bytes R7 R6 R5 R4 R3 R2 R1 R0 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D...

Page 57: ...FR This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit External RAM 8 192 Bytes Indirect Addressing LCD Display RAM 0000H 003FH 0040H 1FFFH 40CFH 4000H E...

Page 58: ...T0CR T0CNT T0DR T0CDR TIFLAG PLLCR PADB 0C8H OSCCR P7IO EIPOL4L EIPOL4H P0DB P1DB P46DB P9DB 0C0H P7 P6IO EIPOL0L EIPOL0H EIPOL2L EIPOL2H EIPOL3L EIPOL3H 0B8H P6 P5IO EIFLAG0 EIFLAG1 EIFLAG2 EIFLAG3...

Page 59: ...DRL T5ADRH T5BDRL T5BDRH SPI2SRL SPI2SRH 4078H T4CRL T4CRH T4ADRL T4ADRH T4BDRL T4BDRH SPI2DR 4070H UART4CR1 UART4CR2 UART4CR3 UART4ST UART4BD UART4DR 4068H UART3CR1 UART3CR2 UART3CR3 UART3ST UART3BD...

Page 60: ...Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register WDTCNT R 0 0 0 0 0 0 0 0 8FH Watch Timer Control Register WTCR R W 0 0 0 0 0 0 0 90H P2 Data Register P2 R W 0 0 0 0 0 0 0 0 91H Exte...

Page 61: ...0 0 0 AFH PA Pull up Resistor Selection Register PAPU R W 0 0 0 0 0 B0H P5 Data Register P5 R W 0 0 0 0 0 0 0 0 B1H P4 Direction Register P4IO R W 0 0 0 0 0 0 0 0 B2H P0 Direction Register P0IO R W 0...

Page 62: ...0 0 0 CEH P46 Debounce Enable Register P46DB R W 0 0 0 0 0 CFH P9 Debounce Enable Register P9DB R W 0 0 0 0 0 D0H Program Status Word Register PSW R W 0 0 0 0 0 0 0 0 D1H P8 Direction Register P8IO R...

Page 63: ...lection Register P3PU R W 0 0 0 0 0 0 0 0 EEH P4 Pull up Resistor Selection Register P4PU R W 0 0 0 0 0 0 0 0 EFH P5 Pull up Resistor Selection Register P5PU R W 0 0 0 0 0 0 0 0 F0H B Register B R W 0...

Page 64: ...Register SPI3SR R W 0 0 0 0 0 4010H P0 Open drain Selection Register P0OD R W 0 0 0 0 0 0 0 0 4011H P1 Open drain Selection Register P1OD R W 0 0 0 0 0 0 0 0 4012H P2 Open drain Selection Register P2O...

Page 65: ...P8 Function Selection Register P8FSR R W 0 0 0 0 0 0 0 0 402DH P9 Function Selection Register P9FSR R W 0 0 0 402EH PA Function Selection Register PAFSR R W 0 0 0 0 0 402FH PB Function Selection Regi...

Page 66: ...R W 0 0 0 0 0 0 0 0 404AH USI1 Baud Rate Generation Register USI1BD R W 1 1 1 1 1 1 1 1 404BH USI1 SDA Hold Time Register USI1SDHR R W 0 0 0 0 0 0 0 1 404CH USI1 Data Register USI1DR R W 0 0 0 0 0 0...

Page 67: ...CH UART3 Baud Rate Generation Register UART3BD R W 1 1 1 1 1 1 1 1 406DH UART3 Data Register UART3DR R W 0 0 0 0 0 0 0 0 406EH Reserved 406FH Reserved 4070H UART4 Control Register 1 UART4CR1 R W 0 0 0...

Page 68: ...408FH SPI2 Control High Register SPI2CRH R W 0 0 0 0 0 0 0 0 4090H Timer 7 Control Register T7CR R W 0 0 0 0 0 0 0 0 4091H Timer 7 Counter Register T7CNT R 0 0 0 0 0 0 0 0 4091H Timer 7 Data Register...

Page 69: ...Generator Counter Low Register PWMCNTL R 0 0 0 0 0 0 0 0 40AFH PWM Generator Counter High Register PWMCNTH R 0 0 40B0H FADPCM Decoder Control Register DECCR R W 0 0 0 0 0 0 0 0 40B1H FADPCM Decoder F...

Page 70: ...Converter Buffer Low Register DACBRL R 0 0 0 0 0 0 0 0 40C5H D A Converter Buffer High Register DACBRH R 0 0 0 0 0 0 0 0 40C6H Voice Prompt Control Register VPCR R W 0 0 0 0 0 0 0 0 40C7H Serial Flash...

Page 71: ...value 07H SP Stack Pointer XSP Extended Stack Pointer 91H 7 6 5 4 3 2 1 0 XSP R W R W R W R W R W R W R W R W Initial value 07H XSP Extended Stack Pointer The XSP is a high of stack pointer when XSPE...

Page 72: ...ue 00H DPH1 Data Pointer Register High 1 85H 7 6 5 4 3 2 1 0 DPH1 R W R W R W R W R W R W R W R W Initial value 00H DPH1 Data Pointer High 1 PSW Program Status Word Register D0H 7 6 5 4 3 2 1 0 CY AC...

Page 73: ...inter Watch Register Low Byte F4H 7 6 5 4 3 2 1 0 SPWRL R W R W R W R W R W R W R W R W Initial value 00H SPWRL Stack Pointer Watch Low SPWRH Stack Pointer Watch Register High Byte F5H 7 6 5 4 3 2 1 0...

Page 74: ...atch low register SWARL If the values are same SP 7 0 SWARL 7 0 the SPOVIFR bit is set to 1b At this time the XSP and SWARH registers are don t care 2 When the XSPEN bit of the XSPCR register is 1b Th...

Page 75: ...when Memory Bank used MCB 18 16 Memory Constant Bank with MEX3 7 IB 19 16 Interrupt Bank NOTE 1 This register controls the current memory bank numbers for interrupt service routine code and for memory...

Page 76: ...MEXSP3 MEXSP2 MEXSP1 MEXSP0 R W R W R W R W R W R W R W Initial value 00H MEXSP 6 0 Memory Extension Stack Pointer NOTE 1 This register is the memory extension stack pointer It provides for a stack de...

Page 77: ...ofPx to input mode Set bits of this register will make the pin to output mode Almost bits are cleared by a system reset but some bits are set by a system reset 9 2 3 Pull up Resistor Selection Registe...

Page 78: ...R W 00H P1 Function Selection High Register P1FSRL 401EH XSFR R W 00H P1 Function Selection Low Register P2 90H R W 00H P2 Data Register P2IO B4H R W 00H P2 Direction Register P2OD 4012H XSFR R W 00H...

Page 79: ...tion Register P8OD 4018H XSFR R W 00H P8 Open drain Selection Register P8PU ADH R W 00H P8 Pull up Resistor Selection Register P8FSR 402CH XSFR R W 00H P8 Function Selection Register P9 A1H R W 00H P9...

Page 80: ...7 0 I O Data P0IO P0 Direction Register B2H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O Direction 0 Input 1 O...

Page 81: ...unce of P03Port 0 Disable 1 Enable P02DB Configure Debounce of P02 Port 0 Disable 1 Enable P01DB Configure Debounce of P01 Port 0 Disable 1 Enable P00DB Configure Debounce of P00 Port 0 Disable 1 Enab...

Page 82: ...le when input 1 AN6 Function P0FSR5 P05 Function Select 0 I O Port EINT5 function possible when input 1 AN5 Function P0FSR4 P04 Function Select 0 I O Port EINT4 function possible when input 1 AN4 Func...

Page 83: ...ata P1IO P1 Direction Register B3H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R W R W R W R W R W R W R W Initial value 00H P1IO 7 0 P1 Data I O Direction 0 Input 1 Output NOT...

Page 84: ...14 Port 0 Disable 1 Enable P13DB Configure Debounce of P13 Port 0 Disable 1 Enable P12DB Configure Debounce of P12 Port 0 Disable 1 Enable P11DB Configure Debounce of P11 Port 0 Disable 1 Enable P10DB...

Page 85: ...1FSRH0 R W R W R W R W Initial value 00H P1FSRH3 P17 Function Select 0 I O Port 1 XOUT Function P1FSRH2 P16 Function Select 0 I O Port 1 XIN Function P1FSRH1 P15 Function Select 0 I O Port EINT9 EC6 f...

Page 86: ...PWM6O Function 1 0 SEG61 Function 1 1 Not used P1FSRL 5 4 P12Function Select P1FSRL5 P1FSRL4 Description 0 0 I O Port EINT15 function possible when input 0 1 T5O PWM5O Function 1 0 SEG60 Function 1 1...

Page 87: ...irection Register B4H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R W R W R W R W R W R W R W R W Initial value 00H P2IO 7 0 P2 Data I O Direction 0 Input 1 Output NOTE 1 SS3 EC3 E...

Page 88: ...P26 Function Select 0 I O Port EXTSP0 function possible when input 1 COM6 SEG51 Function P2FSRH2 P25 Function select 0 I O Port TRIG function possible when input 1 COM5 SEG50 Function P2FSRH 1 0 P24 F...

Page 89: ...nput mode for SPI3 When VDD 3V P2FSRL 6 5 P23 Function Select P2FSRL6 P2FSRL5 Description 0 0 I O Port 0 1 SEG48 Function 1 0 T3O PWM3O Function 1 1 EXTSP2 P2FSRL4 P22 Function Select 0 I O Port SS3 f...

Page 90: ...ta P3IO P3 Direction Register B5H 7 6 5 4 3 2 1 0 P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO R W R W R W R W R W R W R W R W Initial value 00H P3IO 7 0 P3 Data I O Direction 0 Input 1 Output NOTE...

Page 91: ...V P3FSRH 6 5 P37 Function Select P3FSRH6 P3FSRH5 Description 0 0 I O Port 0 1 SEG44 Function 1 0 MISO3 Function 1 1 Not used NOTE 1 Refer to the DACIFCR register for the LDACB3 function P3FSRH4 P36 Fu...

Page 92: ...0 1 SEG40 Function 1 0 MISO2 Function 1 1 Not used NOTE 1 Refer to the DACIFCR register for the CSB2 function P3FSRL 5 4 P32 Function Select P3FSRL5 P3FSRL4 Description 0 0 I O Port 0 1 SEG39 Functio...

Page 93: ...I O Data P4IO P4 Direction Register B1H 7 6 5 4 3 2 1 0 P47IO P46IO P45IO P44IO P43IO P42IO P41IO P40IO R W R W R W R W R W R W R W R W Initial value 00H P4IO 7 0 P4 Data I O Direction 0 Input 1 Outpu...

Page 94: ...nfigure Debounce of P44 Port 0 Disable 1 Enable P43DB Configure Debounce of P43 Port 0 Disable 1 Enable NOTE 1 If the same level is not detected on enabled pin three or four times in a row at the samp...

Page 95: ...when input 1 SEG36 Function P4FSRH 5 4 P46 Function Select P4FSRH5 P4FSRH4 Description 0 0 I O Port 0 1 SEG35 Function 1 0 BUZO Function 1 1 Not used P4FSRH 3 2 P45 Function Select P4FSRH3 P4FSRH2 De...

Page 96: ...tion Select P4FSRL4 P4FSRL3 Description 0 0 I O Port EINT10 function possible when input 0 1 SEG32 Function 1 0 T0O PWM0O Function 1 1 Not used P4FSRL2 P42 Function Select 0 I O Port EC2 function poss...

Page 97: ...P5IO P5 Direction Register B9H 7 6 5 4 3 2 1 0 P57IO P56IO P55IO P54IO P53IO P52IO P51IO P50IO R W R W R W R W R W R W R W R W Initial value 00H P5IO 7 0 P5 Data I O Direction 0 Input 1 Output NOTE 1...

Page 98: ...P5FSRH6 P5FSRH5 Description 0 0 I O Port 0 1 SEG25 Function 1 0 RXD1 SCL1 MISO1 Function 1 1 Not used P5FSRH 4 3 P56 Function Select P5FSRH4 P5FSRH3 Description 0 0 I O Port 0 1 SEG24 Function 1 0 TX...

Page 99: ...P53 Function Select P5FSRL5 P5FSRL4 Description 0 0 I O Port 0 1 SEG21 Function 1 0 TXD3 Function 1 1 Not used P5FSRL3 P52 Function Select 0 I O Port RXD3 function possible when input 1 SEG20 Functio...

Page 100: ...H P6 5 0 I O Data P6IO P6 Direction Register C1H 7 6 5 4 3 2 1 0 P65IO P64IO P63IO P62IO P61IO P60IO R W R W R W R W R W R W Initial value 00H P6IO 5 0 P6 Data I O Direction 0 Input 1 Output NOTE 1 EI...

Page 101: ...029H XSFR 7 6 5 4 3 2 1 0 P6FSRH2 P6FSRH1 P6FSRH0 R W R W R W Initial value 00H P6FSRH2 P65 Function Select 0 I O Port RXD2 function possible when input 1 AN11 Function P6FSRH 1 0 P64 Function Select...

Page 102: ...tion possible when input 0 1 AN9 Function 1 0 DAC Function 1 1 Not used P6FSRL 5 4 P62 Function Select P6FSRL5 P6FSRL4 Description 0 0 I O Port EINT17 function possible when input 0 1 AN8 Function 1 0...

Page 103: ...value 00H P7 7 0 I O Data P7IO P7 Direction Register C9H 7 6 5 4 3 2 1 0 P77IO P76IO P75IO P74IO P73IO P72IO P71IO P70IO R W R W R W R W R W R W R W R W Initial value 00H P7IO 7 0 P7 Data I O Directi...

Page 104: ...6 5 4 3 2 1 0 P7FSRH3 P7FSRH2 P7FSRH1 P7FSRH0 R W R W R W R W Initial value 00H P7FSRH3 P77 Function Select 0 I O Port 1 COM0 Function P7FSRH2 P76 Function Select 0 I O Port 1 COM1 Function P7FSRH1 P...

Page 105: ...SRL6 Description 0 0 I O Port 0 1 VLC0 Function 1 0 PWM8CB Function 1 1 SEG4 Function P7FSRL 5 4 P72 Function Select P7FSRL5 P7FSRL4 Description 0 0 I O Port 0 1 VLC1 Function 1 0 PWM8CA Function 1 1...

Page 106: ...value 00H P8 7 0 I O Data P8IO P8 Direction Register D1H 7 6 5 4 3 2 1 0 P87IO P86IO P85IO P84IO P83IO P82IO P81IO P80IO R W R W R W R W R W R W R W R W Initial value 00H P8IO 7 0 P8 Data I O Directi...

Page 107: ...Function Select 0 I O Port 1 SEG17 Function P8FSR6 P86 Function Select 0 I O Port 1 SEG16 Function P8FSR5 P85 Function Select 0 I O Port 1 SEG15 Function P8FSR4 P84 Function Select 0 I O Port 1 SEG14...

Page 108: ...R W R W R W R W Initial value 00H P9 4 0 I O Data P9IO P9 Direction Register D9H 7 6 5 4 3 2 1 0 P94IO P93IO P92IO P91IO P90IO R W R W R W R W R W Initial value 00H P9IO 4 0 P9 Data I O Direction 0 I...

Page 109: ...onfigure Debounce of P91 Port 0 Disable 1 Enable P90DB Configure Debounce of P90 Port 0 Disable 1 Enable NOTE 1 If the same level is not detected on enabled pin three or four times in a row at the sam...

Page 110: ...P9FSR1 P9FSR0 R W R W R W Initial value 00H P9FSR2 P92 Function Select 0 I O Port EINTC function possible when input 1 AN14 Function P9FSR1 P91 Function Select 0 I O Port EINTB SS5 function possible...

Page 111: ...R W R W R W R W Initial value 00H PA 4 0 I O Data PAIO PA Direction Register E1H 7 6 5 4 3 2 1 0 PA4IO PA3IO PA2IO PA1IO PA0IO R W R W R W R W R W Initial value 00H PAIO 4 0 PA Data I O Direction 0 I...

Page 112: ...onfigure Debounce of PA1 Port 0 Disable 1 Enable PA0DB Configure Debounce of PA0 Port 0 Disable 1 Enable NOTE 1 If the same level is not detected on enabled pin three or four times in a row at the sam...

Page 113: ...ort EINTJ function possible when input 1 SEG57 Function PAFSR3 PA3 Function Select 0 I O Port EINTI function possible when input 1 SEG56 Function PAFSR2 PA2 Function Select 0 I O Port EINTH function p...

Page 114: ...ter A4H 7 6 5 4 3 2 1 0 PB2 PB1 PB0 R W R W R W Initial value 00H PB 2 0 I O Data PBIO PB Direction Register E9H 7 6 5 4 3 2 1 0 PB2IO PB1IO PB0IO R W R W R W Initial value 00H PBIO 2 0 PB Data I O Di...

Page 115: ...Selection Register 402FH XSFR 7 6 5 4 3 2 1 0 PBFSR2 PBFSR1 PBFSR0 R W R W R W Initial value 00H PBFSR2 PB2 Function Select 0 I O Port 1 SEG28 Function PBFSR1 PB1 Function Select 0 I O Port 1 SEG27 F...

Page 116: ...1 PD0 R W R W R W R W R W Initial value 00H PD 4 0 I O Data PDIO PD Direction Register F1H 7 6 5 4 3 2 1 0 PD4IO PD3IO PD2IO PD1IO PD0IO R W R W R W R W R W Initial value 00H PDIO 4 0 PD Data I O Dire...

Page 117: ...SR2 PDFSR1 PDFSR0 R W R W R W R W R W Initial value 00H PDFSR4 PD4 Function Select 0 I O Port 1 SEG9 Function PDFSR3 PD3 Function Select 0 I O Port 1 SEG8 Function PDFSR2 PD2 Function Select 0 I O Por...

Page 118: ...e enabled through four pair of interrupt enable registers IE IE1 IE2 and IE3 Each bit of IE IE1 IE2 IE3 register individually enables disables the corresponding interrupt source Overall control is pro...

Page 119: ...EINT11 Pin EINT13 Pin EINT15 Pin EINT17 Pin EINT10 Pin FLAG10 FLAG11 EINT12 Pin FLAG12 FLAG13 EINT14 Pin FLAG14 FLAG15 EINT16 Pin FLAG16 FLAG17 EINT9 Pin FLAG9 EINT18 Pin FLAG18 EIPOL 1 2 2 EIPOL2H EI...

Page 120: ...r 5 T5IFR Timer 4 T4IFR Timer 3 T3IFR Timer 6 T6IFR Emergency Stop EINT11 EIFLAG2 0 EINT13 EINT15 EINT17 EINT10 EINT12 EINT14 EINT16 EIFLAG2 1 EIFLAG2 2 EIFLAG2 3 EIFLAG2 4 EIFLAG2 5 EIFLAG2 6 EIFLAG2...

Page 121: ...upt INT10 IE1 4 11 Maskable 0053H SPI2 Rx FIFO Full Interrupt INT11 IE1 5 12 Maskable 005BH T0 1 2 OVF Match Interrupt INT12 IE2 0 13 Maskable 0063H T3 4 5 6 Match Interrupt INT13 IE2 1 14 Maskable 00...

Page 122: ...instruction it needs 3 9 machine cycles to go to the interrupt service routine The interrupt service task is terminated by the interrupt return instruction RETI Once an interrupt request is generated...

Page 123: ...g of Interrupt Enable Register Case b Interrupt flag Register Figure 10 5 Effective Timing of Interrupt Flag Register Interrupt Flag Register Command Next Instruction Next Instruction After executing...

Page 124: ...han INT1 is occurred Then INT0 is served immediately and then the remain part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be served after the...

Page 125: ...Saving Restore Process Diagram and Sample Source Main Task Saving Register Restoring Register Interrupt Service Task INTxx PUSH PSW PUSH DPL PUSH DPH PUSH B PUSH ACC Interrupt_Processing POP ACC POP B...

Page 126: ...12 1 Interrupt Enable Register IE IE1 IE2 IE3 Interrupt enable register consists of global interrupt control bit EA and peripheral interrupt control bits Total 24 peripherals are able to control inter...

Page 127: ...y 0 High Register IP1L 9AH R W 00H Interrupt Priority 1 Low Register IP1H 9BH R W 00H Interrupt Priority 1 High Register IP2L 9CH R W 00H Interrupt Priority 2 Low Register IP2H 9DH R W 00H Interrupt P...

Page 128: ...t control registers The interrupt register consists of interrupt enable register IE interrupt enable register 1 IE1 interrupt enable register 2 IE2 and interrupt enable register 3 IE3 For external int...

Page 129: ...rrupt bits 0 All Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 0 7 EINT0 EINT7 0 Disable 1 Enable INT4E Enable or Disable USI1 I2C Tx Interrupt 0 Disable 1 Enable...

Page 130: ...Enable or Disable SPI2 Rx FIFO full Interrupt 0 Disable 1 Enable INT10E Enable or Disable USI0 Tx I2C Interrupt 0 Disable 1 Enable INT9E Enable or Disable USI0 Rx Interrupt 0 Disable 1 Enable INT8E E...

Page 131: ...ty Interrupt 0 Disable 1 Enable INT16E Enable or Disable External Interrupt 8 9 18 0 Disable 1 Enable INT15E Enable or Disable FADPCM Decoder and D AC Interrupt 0 Disable 1 Enable INT14E Enable or Dis...

Page 132: ...al interrupt 10 17 EINT10 EINT17 0 Disable 1 Enable INT22E Enable or Disable BIT WDT ADC SP OVF Interrupt 0 Disable 1 Enable INT21E Enable or Disable EINTA EINTJ Interrupt 0 Disable 1 Enable INT20E En...

Page 133: ...5 0 Select IE Interrupt Priority IP0Hx IP0Lx Description 0 0 level 0 lowest 0 1 level 1 1 0 level 2 1 1 level 3 highest IP1L Interrupt Priority 1 Low Register 9AH 7 6 5 4 3 2 1 0 IP1L5 IP1L4 IP1L3 IP1...

Page 134: ...5 0 Select IE Interrupt Priority IP2Hx IP2Lx Description 0 0 level 0 lowest 0 1 level 1 1 0 level 2 1 1 level 3 highest IP3L Interrupt Priority 3 Low Register 9EH 7 6 5 4 3 2 1 0 IP3L5 IP3L4 IP3L3 IP3...

Page 135: ...4 3 2 1 0 POL7 POL6 POL5 POL4 R W R W R W R W R W R W R W R W Initial value 00H EIPOL0H 7 0 External interrupt EINT7 EINT6 EINT5 EINT4 polarity selection POLn 1 0 Description 0 0 No interrupt at any e...

Page 136: ...nterrupt occurs this bit becomes 1 The flag is cleared only by writing a 0 to the bit So the flag should be cleared by software Writing 1 has no effect 0 T4 Interrupt no generation 1 T4 Interrupt gene...

Page 137: ...1 0 POL17 POL16 POL15 POL14 R W R W R W R W R W R W R W R W Initial value 00H EIPOL2H 7 0 External interrupt EINT17 EINT16 EINT15 EINT14 polarity selection POLn 1 0 Description 0 0 No interrupt at an...

Page 138: ...High Register C7H 7 6 5 4 3 2 1 0 POLE R W R W Initial value 00H EIPOL3H 1 0 External interrupt EINTE polarity selection POLE 1 0 Description 0 0 No interrupt at any edge 0 1 Interrupt on rising edge...

Page 139: ...High Register CBH 7 6 5 4 3 2 1 0 POLJ R W R W Initial value 00H EIPOL4H 1 0 External interrupt EINTJ polarity selection POLJ 1 0 Description 0 0 No interrupt at any edge 0 1 Interrupt on rising edge...

Page 140: ...main sub clock can be also obtained from the external oscillator In this case it is necessary to put the external clock signal into the XIN SXIN pin and open the XOUT SXOUT pin The default system cloc...

Page 141: ...Sub OSC fSUB STOP Mode SCLKE WT 2 SCLK 1 0 256 Internal RC OSC 16MHz STOP Mode IRCE PLL fPLL BIT clock fx 4096 fx 1024 fx 128 fx 16 M U X BITCK 1 0 fIRC 1 2 1 4 1 8 M U X 1 16 1 32 3 IRCS 2 0 Figure 1...

Page 142: ...or SCCR System and Clock Control Register 8AH 7 6 5 4 3 2 1 0 PSAVE SCLK1 SCLK0 R W R W R W Initial value 00H PSAVE Power Save Mode Control Bit 0 Normal circuit for sub oscillator 1 Power saving circu...

Page 143: ...2 0 5MHz 0 0 1 INT RC 16 1MHz 0 1 0 INT RC 8 2MHz 0 1 1 INT RC 4 4MHz 1 0 0 INT RC 2 8MHz Other values Not used IRCE Control the Operation of the Internal RC Oscillator 0 Enable operation of INT RC OS...

Page 144: ...tus Bit 0 PLL currently in unlocked state 1 PLL currently in locked state P1DIV 1 0 PLL Post 1 Divider Selection Bits 49 152MHz P1DIV1 P1DIV0 Description 0 0 fVCO 3 16 384MHz 0 1 fVCO 4 12 888MHz 1 0...

Page 145: ...It also provides a basic interval timer interrupt BITIFR The MC97F60128 has these basic interval timer BIT features During Power On BIT gives a stable clock generation time On exiting Stop mode BIT g...

Page 146: ...n The basic interval timer register consists of basic interval timer counter register BITCNT and basic interval timer control register BITCR If BCLR bit is set to 1 BITCNT becomes 0 and then counts up...

Page 147: ...BITCK 1 0 Select BIT clock source BITCK1 BITCK0 Description 0 0 fx 4096 0 1 fx 1024 1 0 fx 128 1 1 fx 16 BITIE Enable or Disable Basic Interval Timer Interrupt 0 Disable 1 Enable BCLR If this bit is...

Page 148: ...s up After 1 machine cycle this bit is cleared to 0 automatically The watchdog timer consists of 8 bit binary counter and the watchdog timer data register When the value of 8 bit binary counter is equ...

Page 149: ...Map Name Address Dir Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R W 00H Watch Dog Timer Control Register Table 11 3 W...

Page 150: ...ister WDTCR Watch Dog Timer Control Register 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL WDTIE WDTCK WDTIFR R W R W R W R W R W R W Initial value 00H WDTEN Control WDT Operation 0 Disable 1 Enable WDTRSON...

Page 151: ...may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to raise resolution In WTDR it can control WT clear and set interval value at write time...

Page 152: ...R can control the clock source WTCK 1 0 interrupt interval WTIN 1 0 and function enable disable WTEN Also there is WT interrupt flag bit WTIFR 11 4 5 Register Description for Watch Timer WTCNT Watch T...

Page 153: ...iting a 0 to the bit So the flag should be cleared by software Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Descript...

Page 154: ...rnal or an external clock source ECn The clock source is selected by clock selection logic which is controlled by the clock selection bits TnCK 2 0 TIMER 0 1 2 clock source fX 2 4 8 32 128 512 2048 an...

Page 155: ...r at the rising edge If the ECn is selected as a clock source by TnCK 2 0 EC0 EC1 EC2 port should be set to the input port by P40IO P41IO P42IO bit P r e s c a l e r fx M U X fx 2 TnCNT 8Bit ECn fx 4...

Page 156: ...f timer 0 1 2 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H The timer 0 1 2 overflow interrupt...

Page 157: ...4AH FFH FEH 00H Tn Match Interrupt Tn Overflow Interrupt TnDR 1 TnDR 4AH Timer n clock Set TnEN TnPWM Tn Match Interrupt 2 TnDR 00H TnPWM Tn Match Interrupt 3 TnDR FFH PWM Mode TnMS 01b Figure 11 10...

Page 158: ...not available According to EIPOL2H L registers setting the external interrupt EINT1n function is chosen Of course the EINT1n pin must be set to an input port TnCDR and TnDR are in the same address In...

Page 159: ...erflow in Capture Mode Where n 0 1 and 2 TnCNT Interrupt Request FLAG1n XXH Interrupt Interval Period FFH 01H FFH 01H YYH 01H Ext EINT1n PIN Interrupt Request TnIFR FFH FFH YYH 00H 00H 00H 00H 00H TnC...

Page 160: ...r n Counter TnDR 8Bit Comparator TnIFR TnO PWMnO 8 bit Timer n Data Register TnCC Clear Match signal Match MUX TnCDR 8Bit Clear TnOVIFR To interrupt block EINT1n POL1n of EIPOL2L FLAG1n EIFLAG2 n To i...

Page 161: ...ure data register TnCDR timer 0 1 2 control register TnCR timer interrupt control register TINTCR and timer interrupt flag register TIFLAG 11 5 8 Register Description for Timer Counter 0 1 2 TnCNT Tim...

Page 162: ...TnMS1 TnMS0 Description 0 0 Timer counter mode TnO toggle at match 0 1 PWM mode The overflow interrupt can occur 1 x Capture mode The match interrupt can occur TnCK 2 0 Select Timer n clock source fx...

Page 163: ...or Disable Timer 2 Match Interrupt 0 Disable 1 Enable T1MIE Enable or Disable Timer 1 Match Interrupt 0 Disable 1 Enable T0MIE Enable or Disable Timer 0 Match Interrupt 0 Disable 1 Enable T2OVIE Enab...

Page 164: ...it becomes 1 The flag is cleared only by writing a 0 to the bit So the flag should be cleared by software Writing 1 has no effect 0 T1 overflow interrupt no generation 1 T1 overflow interrupt generati...

Page 165: ...Timer 3 4 5 6 outputs PWM wave form through PWMnO port in the PPG mode TnEN TnMS 1 0 TnCK 2 0 Timer n 1 00 XXX 16 Bit Timer Counter Mode 1 01 XXX 16 Bit Capture Mode 1 10 XXX 16 Bit PPG Mode one shot...

Page 166: ...3 TnCK 2 0 2 TnMIE TnMS1 TnMS0 TnCC X 0 0 X TnCK2 TnCRL X ADDRESS E2H 4078H 4080H 4088H INITIAL VALUE 0000_0000B TnCK1 TnCK0 TnPOL TnECE TnCNTR X X X X X TnEN To interrupt block TnMIE To other block N...

Page 167: ...EINT1n function is chosen Of course the EINT1n pin must be set as an input port TnEN TnCRH 1 ADDRESS E3H 4079H 4081H 4089H INITIAL VALUE 0000_0000B TnMS1 TnMS0 TnCC 0 1 X TnCK1 TnCRL X ADDRESS E2H 407...

Page 168: ...n Capture Mode where n 3 4 5 and 6 TnCNTH L Interrupt Request FLAG1n XXH Interrupt Interval Period FFFFH 01H FFFFH 01H YYH 01H Ext EINT1n PIN Interrupt Request TnIFR FFFFH FFFFH YYH 00H 00H 00H 00H 00...

Page 169: ...mparator 16 bit Counter TnCNTH TnCNTL 16 bit B Data Register TnBDRH TnBDRL Clear B Match Edge Detector TnECE ECn Buffer Register B Comparator 16 bit A Data Register TnADRH TnADRL TnIFR S W Clear A Mat...

Page 170: ...nADRH L PWMnO A Match 2 TnBDRH L TnADRH L PWMnO A Match 3 TnBDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer n clock Counter TnADRH L Tn Interrupt PWMnO B Match One shot Mode TnMS 10b and Start High T...

Page 171: ...Match Buffer Register A Reload Pulse Generator TnO PWMnO R EINT1n TnCNTR TnEN Clear POL1 n of EIPOL 2H L FLAG1n EIFLAG 2 n S W Clear To interrupt block 2 2 TnMS 1 0 2 P r e s c a l e r fx M U X fx 4 f...

Page 172: ...w Register TnBDRH E7H 407DH 4085H 408DH R W FFH Timer n B Data High Register TnBDRL E6H 407CH 4084H 408CH R W FFH Timer n B Data Low Register Table 11 8 Timer 3 4 5 6 Register Map where n 3 4 5 and 6...

Page 173: ...TnADRL3 TnADRL2 TnADRL1 TnADRL0 R W R W R W R W R W R W R W R W Initial value FFH TnADRL 7 0 Tn A Data Low Byte NOTE 1 Do not write 0000H in the TnADRH TnADRL register when PPG mode TnBDRH Timer n B...

Page 174: ...or Disable Timer n Match Interrupt 0 Disable 1 Enable TnMS 1 0 Control Timer n Operation Mode TnMS1 TnMS0 Description 0 0 Timer counter mode TnO toggle at A match 0 1 Capture mode The A match interrup...

Page 175: ...fx 128 0 1 0 fx 32 0 1 1 fx 8 1 0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 External clock ECn TnPOL TnO PWMnO Polarity Selection 0 Start High TnO PWMnO is low level at disable 1 Start Low TnO PWMnO is high...

Page 176: ...election bits T7CK 2 0 T8CK 3 0 Also the timer counter 8 can use more clock sources than timer counter 7 TIMER 7 clock source fX 2 4 8 32 128 512 2048 and EC7 TIMER 8 clock source fX 1 2 4 8 16 32 64...

Page 177: ...a clock source by T7CK 2 0 EC7 port should be set to the input port by P63IO bit Timer 8 can t use the external EC7 clock T7EN T7CR 1 ADDRESS 4090H XSFR INITIAL VALUE 0000_0000B T7IE T7MS T7CK2 T7CK1...

Page 178: ...SB 8 bit the timer 8 is MSB 8 bit The external clock EC7 counts up the timer at the rising edge f the EC7 is selected as a clock source by T7CK 2 0 EC7 port should be set to the input port by P63IO bi...

Page 179: ...y cleared by match signal This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer The capture result is loaded into T7CAPR...

Page 180: ...ar Match T7CAPR 8Bit Clear EINT17 EIPOL2H 7 6 FLAG17 EIFLAG2 7 S W Clear To interrupt block 2 T7MS T7ST 8 bit Timer 7 Capture Register T8CNT 8Bit 4 T8CK 3 0 8 bit Timer 8 Counter T8DR 8Bit Comparator...

Page 181: ...fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T7CK 2 0 T7CN 16 bit Timer 7 Counter T8DR T7DR 16Bit Comparator T7IFR T7O 16 bit Timer 7 Data Register S W Clear Clear Match T8CAPR T7CAPR 16Bit Clear EINT17 E...

Page 182: ...ADRL X Source Clock Resolution Frequency T8CK 3 0 0001 250ns T8CK 3 0 0010 500ns T8CK 3 0 0100 2us 10 Bit 3 9kHz 1 95kHz 0 49kHz 9 Bit 7 8kHz 3 9kHz 0 98kHz 8 Bit 15 6kHz 7 8kHz 1 95kHz 7 Bit 31 2kHz...

Page 183: ...NT 10 bit A Data Register T8ADRH T8ADRL Control Up Down Comparator T8PPRH T8PPRL 10Bit Period Match PWM Output Control A ch PWM8AA T8CN 4 T8CK 3 0 T7 Clock Source fx 128 fx 256 fx 1024 fx 2048 fx 4096...

Page 184: ...LUE 0000_0000B PAAOE PABOE PBAOE PBBOE PCAOE PCBOE X X X X X X HZCLR T8PCR3 X ADDRESS 4095H XSFR INITIAL VALUE 0000_0000B POLBO POLAA POLAB POLBA POLBB POLCA POLCB X X X X X X X 16BIT T8CR 0 ADDRESS 4...

Page 185: ...7 03 02 01 00 05 04 Source Clock fx 06 Duty Cycle 1 05H X2us 12us Duty Cycle 1 05H X2us 12us Duty Cycle 1 05H X2us 12us Period Cycle 1 0EH X2us 32us 31 25kHz Period Cycle 1 0AH X2us 22us 45 5kHz Write...

Page 186: ...cycle of timer clock to get the right output waveform Phase correction Frequency correction On operating PWM it is possible that it is changed the phase and the frequency by using BMOD bit back to ba...

Page 187: ...3 Overflow INT Overflow INT Bottom INT Overflow INT Interrupt Timing T8CNT 00 01 02 03 04 P61 PWM8AA POLAA 1 T8CR 03H 2us T8PPRH 00H T8PPRL 0BH T8ADRH 00H T8ADRL 05H 09 08 07 06 05 0A 0B 0B 0A 06 07 0...

Page 188: ...to stop PWM operation by the software During PHLT bit being 1 PWM output becomes a reset value and internal counter becomes reset as 0 Without changing PWM setting temporarily it is able to stop PWM I...

Page 189: ...at the inversion outputs of A B C channel have the same A ch output waveform According to POLAA BB CC it is able to control the inversion of outputs Figure 11 35 Example of Force Drive All Channel wit...

Page 190: ...BA BB output of the B channel duty register a CA CB output of the C channel duty register are controlled respectively If the UALL bit is set to 1 it is updated B C channel duty at the same time when...

Page 191: ...e so the duty is reduced as the time delay In POLAA BA CA setting to 0 the delay is applied to the falling edge In POLAA BA CA setting to 1 the delay is applied to the rising edge It can produce a pai...

Page 192: ...ESS 40A0H XSFR INITIAL VALUE 0000_0000B FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T8PCR2 0 X X X X X X HZCLR POLBO POLAA POLAB POLBA POLBB POLCA T8PCR3 X X 1 1 X X X X T8DLYAA3 T8DLYAA2 T8DLYAA1 T8DLY...

Page 193: ...7 Capture Register T8CNT 8Bit 4 T8CK 3 0 8 bit Timer 8 Counter T8DR 8Bit Comparator To interrupt block T8O 8 bit Timer 8 Data Register Clear Match T8CAPR 8Bit Clear EINT18 EIPOL0L 3 2 FLAG18 EIFLAG1...

Page 194: ...8 fx 1 Comparator 10 bit Counter 2Bit T8CNT 10 bit A Data Register T8ADRH T8ADRL Control Up Down Comparator T8PPRH T8PPRL 10Bit Period Match PWM Output Control A ch PWM8AA T8CN 4 T8CK 3 0 T7 Clock Sou...

Page 195: ...gister T8PPRL 4098H XSFR R W FFH Timer 8 PWM Period Low Register T8PPRH 4099H XSFR R W 00H Timer 8 PWM Period High Register T8ADRL 409AH XSFR R W 7FH Timer 8 PWM A Duty Low Register T8ADRH 409BH XSFR...

Page 196: ...Case Timer mode only 4091H XSFR 7 6 5 4 3 2 1 0 T7CNT7 T7CNT6 T7CNT5 T7CNT4 T7CNT3 T7CNT2 T7CNT1 T7CNT0 R R R R R R R R Initial value 00H T7CNT 7 0 T7 Counter T7DR Timer 7 Data Register Write Case 409...

Page 197: ...e 0 Timer counter mode T7O toggle at match 1 Capture mode the match interrupt can occur T7CK 2 0 Select Timer 7 clock source fx is main system clock frequency T7CK2 T7CK1 T7CK0 Description 0 0 0 fx 2...

Page 198: ...d timer 8 interrupt mask register T8MSK 11 7 12 Register Description for Timer Counter 8 T8PPRH Timer 8 PWM Period High Register 6 ch PWM mode only 4099H XSFR 7 6 5 4 3 2 1 0 T8PPRH1 T8PPRH0 R W R W I...

Page 199: ...mer 8 PWM C Duty Low Register 6 ch PWM mode only 409EH XSFR 7 6 5 4 3 2 1 0 T8CDRL7 T8CDRL6 T8CDRL5 T8CDRL4 T8CDRL3 T8CDRL2 T8CDRL1 T8CDRL0 R W R W R W R W R W R W R W R W Initial value 7FH T8CDRL 7 0...

Page 200: ...d Capture mode only 40A3H XSFR 7 6 5 4 3 2 1 0 T8DR7 T8DR6 T8DR5 T8DR4 T4DR3 T8DR2 T8DR1 T8DR0 R W R W R W R W R W R W R W R W Initial value FFH T8DR 7 0 T8 Data T8CAPR Timer 8 Capture Data Register R...

Page 201: ...Pause Continue 0 Temporary count stop 1 Continue count T8ST Control Timer 8 Start Stop 0 Counter stop 1 Clear counter and start T8CK 3 0 Select Timer 8 clock source fx is main system clock frequency...

Page 202: ...K input pin Where x A B and C BMOD Control Back to Back Mode Operation 0 Disable back to back mode up count only 1 Enable back to back mode up down count only PHLT Control Timer 8 PWM Operation 0 Run...

Page 203: ...8xB pins are output according to the only T8ADR registers Where x A B and C PAAOE Select Channel PWM8AA Operation 0 Disable PWM8AA output 1 Enable PWM8AA output PABOE Select Channel PWM8AB Operation 0...

Page 204: ...ng when disable POLAB POLBB POLCB bits where x A B and C POLAA Configure PWM8AA Channel Polarity 0 Start at high level This pin is low level when disable 1 Start at low level This pin is high level wh...

Page 205: ...1 has no effect 0 PWM B ch match no occurrence 1 PWM B ch match occurrence ICMC Timer 8 PWM C ch Match Interrupt Status Write 0 to this bit for clear Write 1 has no effect 0 PWM C ch match no occurren...

Page 206: ...be enabled or disabled by TRIGRS 1 0 bits The delay time is programmable with the 10 bit PWM generator delay data register PWMDLYDR The EXTSP0 EXTSP1 and EXTSP2 pins can be selected for shot stop or...

Page 207: ...dge signal comes from the TRIG pin during the counting the counter will be cleared to 000H and the 10 bit PWM generator will be restarted But if there is no a valid falling edge signal of the TRIG pin...

Page 208: ...erator in the 10 bit PWM one shot mode with auto enable is automatically enabled as PWMEN bit set to 1 by a valid falling edge of the TRIG pin even if the operation stop Of course The EMGIFR bit shoul...

Page 209: ...d the 10 bit PWM generator will be restarted X 1 2 4 1 2 4 5 1 2 PWM clock Counter PWMADRH L PWM Interrupt PWMOUT Match PWMOUT signal without delay Start Low PWMPOL 1b and without delay TRIGRS 10b Set...

Page 210: ...2b 0 3 13 13 10 7 TRIG Input 6 Tst 5 Filtering Time NFILDR x4 fpwm Invalid Trigger Figure 11 45 Timing Chart of Noise Filter Function 1 2 4 1 2 4 0 2 3 PWM clock Counter PWMADRH L PWM Interrupt PWMOU...

Page 211: ...0 0 PWM clock Counter PWMADRH L EMG Interrupt PWMOUT Emergency Stop by the falling edge trigger of the selected EXTSP0 1 2 pins Start Low PWMPOL 1b 0 0 0 10 0 0 TRIG Input 0 Tst Emergency Stop Input I...

Page 212: ...interrupt block POVIE S W Clear TRGIFR To interrupt block TRGIE S W Clear NOTE 1 The PWMEN bit is automatically cleared to 0b after an overflow of the 10 bit counter occurs at a PWM one shot mode 2 Th...

Page 213: ...M Generator Delay Data Register NFILDR 40A7H XSFR R W 0FH PWM Generator Noise Filter Data Register PGINTCR 4066H XSFR R W 00H PWM Generator Interrupt Control Register PGIFLAG 4067H XSFR R W 00H PWM Ge...

Page 214: ...PWMADR6 PWMADR5 PWMADR4 PWMADR3 PWMADR2 PWMADR1 PWMADR0 R W R W R W R W R W R W R W R W Initial value FFH PWMADR 7 0 PWM Generator A Data Low Byte PWMBDRH PWM Generator B Data High Register 40ADH XSF...

Page 215: ...R R R R R R R R Initial value 00H PWMCNT 7 0 PWM Generator Counter Low Byte PWMDLYDR PWM Generator Delay Data Register 40A6H XSFR 7 6 5 4 3 2 1 0 PWMDLY7 PWMDLY6 PWMDLY5 PWMDLY4 PWMDLY3 PWMDLY2 PWMDLY...

Page 216: ...gger If a shot stop occurs the PWMOUT pin is held for the current PWM cycle to low level when PWMPOL bit is 0 and high level when PWMPOL bit is 1 1 0 Enable emergency stop The PWMOUT pin can be stoppe...

Page 217: ...2 1 1 1 fx 1 PWMPOL PWM Output Polarity Selection 0 Start High PWMOUT is low level at disable 1 Start Low PWMOUT is high level at disalbe PWMMD 1 0 PWM Generator Operation Mode PWMMD1 PWMMD0 Descripti...

Page 218: ...e bit So the flag should be cleared by software Write 1 has no effect 0 PWM generator overflow interrupt no generation 1 PWM generator overflow interrupt generation EMGIFR When emergency stop interrup...

Page 219: ...81 0 391 0 195 8 6 944 3 472 1 736 0 868 40 1 524 0 762 0 381 0 191 9 6 250 3 125 1 563 0 781 41 1 488 0 744 0 372 0 186 10 5 682 2 841 1 420 0 710 42 1 453 0 727 0 363 0 182 11 5 208 2 604 1 302 0 65...

Page 220: ...ductor Co Ltd 11 9 2 Overview Pre scaler fx M U X fx 2 Counter fx 4 fx 8 3 BUCK 2 0 6 bit Up Counter BUZDR Comparator F F Clear fx 1 Match BUZO BUZEN fSUB fx 16 fx 32 fx 64 DIV 6 2 fBUZ Figure 11 49 B...

Page 221: ...R3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDIV 1 0 Buzzer Clock Divider BUZDIV1 BUZDIV0 Description 0 0 fBUZ 8 0 1 fBUZ 16 1 0 fBUZ 32 1 1 fBUZ 64 BUZDR 5 0 These bit...

Page 222: ...ta transfer 11 10 2 Block Diagram P r e s c a l e r fx M U X fx 4 fx 8 fx 32 fx 64 fx 128 fx 16 fx 2 SCK Control SPI2MS SCK2 3 SPI2CR 2 0 M U X SPI2MS CPHA2 Edge Detector CPOL2 SPI Control Circuit SPI...

Page 223: ...SS2 pin function 1 When the SPI 2 is configured as a Slave the SS2 pin is always input If LOW signal come into SS2 pin the SPI 2 logic is active And if HIGH signal come into SS2 pin the SPI 2 logic i...

Page 224: ...CK2 CPOL2 1 MISO2 MOSI2 Output MOSI2 MISO2 Input SCK2 CPOL2 0 SS2 SPI2IFR Figure 11 51 SPI 2 Transmit Receive Timing Diagram at CPHA 0 SCK2 CPOL2 1 MISO2 MOSI2 Output MOSI2 MISO2 Input D0 D1 D2 D3 D4...

Page 225: ...PI 2 Register Map 11 10 7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register SPI2CRH L SPI 2 status register SPI2SRH L and SPI 2 data register SPI2DR 11 10 8 Register Des...

Page 226: ...sion 1 Collision SS_HIGH2 When the SS2 pin is configured as input if HIGH signal comes into the pin this flag bit will be set 0 Cleared when 0 is written 1 No effect when 1 is written FXCH2 SPI 2 port...

Page 227: ...curs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Write 1 has no effect 0 SPI2 Rx FIFO full Interrupt no generation 1 SPI2 Rx FIFO full Interrupt generation...

Page 228: ...CPHA2 This two bits control the serial clock SCK2 mode Clock polarity CPOL2 bit determine SCK2 s value at idle mode Clock phase CPHA2 bit determine if data are sampled on the leading or trailing edge...

Page 229: ...TR2 R W R W Initial value 00H FIFOC SPI2 Tx Rx FIFO and Pointer Clear Bit 0 No effect 1 Clear all Tx Rx FIFO Pointer and Control signal Stop transfer MSTR2 SPI2 Master Start Bit 0 No effect 1 Start SP...

Page 230: ...mode can select serial clock SCK3 polarity phase and whether LSB first data transfer or MSB first data transfer 11 11 2 Block Diagram P r e s c a l e r fx M U X fx 4 fx 8 fx 32 fx 64 fx 128 fx 16 fx...

Page 231: ...4 SS3 pin function 1 When the SPI 3 is configured as a Slave the SS3 pin is always input If LOW signal come into SS3 pin the SPI 3 logic is active And if HIGH signal come into SS3 pin the SPI 3 logic...

Page 232: ...CK3 CPOL3 1 MISO3 MOSI3 Output MOSI3 MISO3 Input SCK3 CPOL3 0 SS3 SPI3IFR Figure 11 54 SPI 3 Transmit Receive Timing Diagram at CPHA 0 SCK3 CPOL3 1 MISO3 MOSI3 Output MOSI3 MISO3 Input D0 D1 D2 D3 D4...

Page 233: ...p 11 11 7 SPI 3 Register Description The SPI 3 register consists of SPI 3 control register SPI3CR SPI 3 status register SPI3SR and SPI 3 data register SPI3DR 11 11 8 Register Description for SPI 3 SPI...

Page 234: ...0 SPI 3 Interrupt no generation 1 SPI 3 Interrupt generation WCOL3 This bit is set if any data are written to the data register SPI3DR during transfer This bit is cleared when the status register SPI3...

Page 235: ...A3 This two bits control the serial clock SCK3 mode Clock polarity CPOL3 bit determine SCK3 s value at idle mode Clock phase CPHA3 bit determine if data are sampled on the leading or trailing edge of...

Page 236: ...omplete UART2 3 4 has baud rate generator transmitter and receiver The baud rate generator for asynchronous operation The Transmitter consists of a single write buffer a serial shift register parity g...

Page 237: ...TXDn Tx Control Stop bit Generator M U X UnPM1 Parity Generator Transmit Shift Register TXSR UARTnDR Tx UnPM0 I N T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn UDRIEn UDREn Empty signal To interr...

Page 238: ...mitter and receiver Following table shows equations for calculating the baud rate in bps Operating Mode Equation for Calculating Baud Rate Normal Mode U2Xn 0 Baud Rate fx 16 UARTnBD 1 Double Speed Mod...

Page 239: ...he stop bit A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an i...

Page 240: ...ettings of control registers If the 9 bit characters are used the ninth bit must be written to the UnTX8 bit in UARTnCR3 register before it is loaded to the transmit buffer UARTnDR register 11 12 8 Tr...

Page 241: ...set before serial reception 11 12 12 Receiving Rx data The receiver starts data reception when it detects a valid start bit LOW on RXDn pin Each bit after start bit is sampled at pre defined baud rate...

Page 242: ...first stop bit The FEn flag is 0 when the stop bit was correctly detected as 1 and the FE flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync c...

Page 243: ...and this removes the noise of RXDn pin The next figure illustrates the sampling process of the start bit of an incoming frame The sampling rate is 16 times of the baud rate in normal mode and 8 times...

Page 244: ...ceived bit is considered to a logic 0 and if more than 2 samples have high levels the received bit is considered to a logic 1 The data recovery process is then repeated until a complete frame is recei...

Page 245: ...egister Map where n 2 3 and 4 11 12 18 UART Register Description UART2 3 4 module consists of UART2 3 4 baud rate generation register UARTnBD UART2 3 4 data register UARTnDR UART2 3 4 control register...

Page 246: ...n to the UARTnDR register Reading the UARTnDR register returns the contents of the Receive Buffer Write this register only when the UDREn flag is set UARTnCR1 UARTn Control Register 1 4060H 4068H 4070...

Page 247: ...use polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for Wake in STOP mode When device is in stop mode if RXDn goes to LOW level an interrupt can be requested to wake up s...

Page 248: ...est mode 0 Normal operation 1 Loop Back mode USBSn Selects the length of stop bit 0 1 Stop Bit 1 2 Stop Bit UnTX8 The ninth bit of data frame in UARTn Write this bit first before loading the UARTnDR r...

Page 249: ...e read The RXCn flag can be used to generate a RXCn interrupt Write 1 has no effect 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag i...

Page 250: ...00 95 0 0 103 0 2 191 0 0 4800 47 0 0 51 0 2 95 0 0 9600 23 0 0 25 0 2 47 0 0 14 4k 15 0 0 16 2 1 31 0 0 19 2k 11 0 0 12 0 2 23 0 0 28 8k 7 0 0 8 3 5 15 0 0 38 4k 5 0 0 6 7 0 11 0 0 57 6k 3 0 0 3 8 5...

Page 251: ...ta register USI0 1 SDA hold time register USI0 1 SCL high period register USI0 1 SCL low period register and USI0 1 slave address register USInCR1 USInCR2 USInCR3 USInCR4 USInST1 USInST2 USInBD USInDR...

Page 252: ...ock generator Transmitter and receiver The clock generation logic consists of synchronization logic for external clock inut used by synchronous or SPI slave operation and the baud rate generator for a...

Page 253: ...ft Register TXSR USInDR USInTX8 Tx USInP 1 0 M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn RXCIEn WAKEIEn WAKEn At Stop mode To interrupt block SCLK fx System...

Page 254: ...ble speed mode is controlled by the DBLSn bit in the USInCR2 register The MASTERn bit in USInCR3 register controls whether the clock source is internal master mode output pin or external slave mode in...

Page 255: ...ynchronous or SPI mode is used the SCKn pin will be used as either clock input slave or clock output master Data sampling and transmitter is issued on the different edge of SCKn clock each other For e...

Page 256: ...op bit A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an idle s...

Page 257: ...it will transfer one complete frame according to the settings of control registers If the 9 bit characters are used in asynchronous or synchronous operation mode the ninth bit must be written to the U...

Page 258: ...input pin in slave mode or can be configured as SSn output pin in master mode This can be done by setting USInSSEN bit in USnCR3 register 11 13 15 USI0 1 UART Receiving Rx data When UART is in synchro...

Page 259: ...The FEn flag is 0 when the stop bit was correctly detected as 1 and the FEn flag is 1 when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync conditions betwe...

Page 260: ...s removes the noise of RXDn pin The next figure illustrates the sampling process of the start bit of an incoming frame The sampling rate is 16 times of the baud rate in normal mode and 8 times the bau...

Page 261: ...considered to a logic 0 and if more than 2 samples have high levels the received bit is considered to a logic 1 The data recovery process is then repeated until a complete frame is received including...

Page 262: ...compatibility to other SPI devices 11 13 21 USI0 1 SPI Clock Formats and Timing To accommodate a wide variety if synchronus serial peripherals from different manufacturers the USI0 1 has a clock polar...

Page 263: ...d MOSIn inputs respectively At the second SCKn edge the USI0 1 shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave respectively Unlike the case of CPHAn 1 when...

Page 264: ...out to the MOSIn and MISOn output of the master and slave respectively When CPHAn 1 the slave s SSn input is not required to go to its inactive high level between transfers Because the SPI logic reus...

Page 265: ...I N T E R N A L B U S L I N E M U X LOOPSn TXCn TXCIEn DRIEn DREn Empty signal To interrupt block INT_ACK Clear RXCn Baud Rate Generator USInBD TXEn SCLK fx System clock MISOn MOSIn M U X MASTERn D E...

Page 266: ...standard Multi master operation Up to 400kHz data transfer read speed 7 bit address Both master and slave operation Bus busy detection 11 13 24 USI0 1 I2C Bit Transfer The data on the SDAn line must b...

Page 267: ...ART conditions are functionally identical Figure 11 73 START and STOP Condition USIn where n 0 and 1 11 13 26 USI0 1 I2C Data Transfer Every byte put on the SDAn line must be 8 bits long The number of...

Page 268: ...where n 0 and 1 11 13 28 USI0 1 I2C Synchronization Arbitration Clock synchronization is performed using the wired AND connection of I2C interfaces to the SCLn line This means that a HIGH to LOW tran...

Page 269: ...leared when all interrupt source bits in the USInST2 register are cleared to 0b When I2C interrupt occurs the SCLn line is hold LOW until clearing 0b all interrupt source bits in USInST2 register When...

Page 270: ...vice When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLOSTn...

Page 271: ...DR 2 Master STOP data transfer even if it receives ACK signal from slave In this case set the STOPCn bit in USInCR4 3 Master transmits repeated START condition with not checking ACK signal In this cas...

Page 272: ...bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in idle state or can be operate as an addressed slave To operate as a slave when the MLOSTn bit in USInST2 is...

Page 273: ...s detected master terminates data transfer In this case set the STOPCn bit in USInCR4 4 No ACK signal is detected and master transmits repeated START condition In this case load SLAn R W into the USIn...

Page 274: ...ther START condition Else if the address equals to USInSLA 6 0 bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to US...

Page 275: ...ART condition Else if the address equals to SLAn bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to SLAn bits when t...

Page 276: ...ess Register USInSAR General Call And Address Detector USInGCE STOP START Condition Generator STOPCn STARTCn ACK Signal Generator ACKnEN RXACKn GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn Interrupt...

Page 277: ...4 USI0 1 Register Map where n 0 and 1 11 13 36 Register Description USI0 1 module consists of USI0 1 baud rate generation register USInBD USI0 1 data register USInDR USI0 1 SDA hold time register USIn...

Page 278: ...0 The register is used to control SDAn output timing from the falling edge of SCLn in I2C mode NOTE 1 That SDA is changed after tSCLK X USInSDHR In master mode load half the value of USInSCLR to this...

Page 279: ...SCLK the system clock and the period is calculated by the formula tSCLK X 4 X USInSCLR 2 where tSCLK is the period of SCLK USInSAR USI0 1 Slave Address Register For I2C mode 403FH 404FH XSFR n 0 and 1...

Page 280: ...t 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORDn This bit in the same bit position with USInS1 The MSB of the data byte is transmitted first when set to 1 and th...

Page 281: ...t from RXCn is inhibited use polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXDn goes to low level an in...

Page 282: ...while UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USInSSEN This bit controls the SSn pin operation only SPI mode 0 Disable 1 Enable The SSn pin shoul...

Page 283: ...IICnIE Interrupt Enable bit for I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACKnEN Controls ACK signal Generation at ninth SCL period 0 No ACK signal is generated...

Page 284: ...to generate a RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin is detected low while the CPU i...

Page 285: ...0 No STOP condition is detected 1 STOP condition is detected SSELn NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as a slave 1 I2C is addressed by other master and ac...

Page 286: ...USI1BD ERROR 2400 95 0 0 103 0 2 191 0 0 4800 47 0 0 51 0 2 95 0 0 9600 23 0 0 25 0 2 47 0 0 14 4k 15 0 0 16 2 1 31 0 0 19 2k 11 0 0 12 0 2 23 0 0 28 8k 7 0 0 8 3 5 15 0 0 38 4k 5 0 0 6 7 0 11 0 0 57...

Page 287: ...set to xxx The register ADCDRH and ADCDRL contains the results of the A D conversion When the conversion is completed the result is loaded into the ADCDRH and ADCDRL the A D conversion status bit AFLA...

Page 288: ...T8 B match event signal T8 C match event signal TRIG 2 0 3 T4 A match signal T5 A match signal T8 overflow event signal AVREF MUX ADSEL 3 0 4 M U X fx 2 fx 4 fx 8 fx 1 CKSEL 1 0 2 ADST T3 A match sign...

Page 289: ...ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 ADCO9 A...

Page 290: ...Low Register Table 11 26 ADC Register Map 11 14 6 ADC Register Description The ADC register consists of A D converter data high register ADCDRH A D converter data low register ADCDRL A D converter co...

Page 291: ...ADDL8 R R R R R R R R Initial value xxH ADDM 11 4 MSB align A D Converter High Result 8 bit ADDL 11 8 LSB align A D Converter High Result 4 bit ADCDRL A D Converter Data Low Register 4000H XSFR 7 6 5...

Page 292: ...has no effect 0 ADC Interrupt no generation 1 ADC Interrupt generation TRIG 2 0 A D Trigger Signal Selection TRIG2 TRIG1 TRIG0 Description 0 0 0 ADST 0 0 1 Timer 3 A match signal 0 1 0 Timer 4 A matc...

Page 293: ...A D Conversion Start 0 No effect 1 Trigger signal generation for conversion start AFLAG A D Converter Operation State This bit is cleared to 0 when the STBY bit is set to 0 or when the CPU is at STOP...

Page 294: ...d signal is one of the Always FADPCM decoder match signal Timer 0 match signal and Timer 1 match signal The signal is selected by the DACRLDS 1 0 bits The programmable gain controller has eleven step...

Page 295: ...How to remove a pop noise when a speaker is turn on Write 05H for 0dB to PGSR register Write 0000H to D A converter data register Clear D A converter buffer register by DACBC bit set to 1b Select one...

Page 296: ...R 15 0 by the following procedure Get the value of the D A converter data register DACDR 15 0 Change the data into a 16 bit signed format Adjust the data by a selected gain Modify the data into a 16 b...

Page 297: ...and 3 Only CPHAn CPOLn 0b CMD3 X MOSIn CSBn SCKn D AC Interface Signal 2 DACIFEN 1b MDSEL 1 Where n 2 and 3 CPHAn CPOLn 0b or CPHAn CPOLn 1b MOSIn CSBn LDACBn CMD2 CMD1 D15 D14 D13 D12 D11 D10 D9 D8...

Page 298: ...12 11 10 9 8 7 6 5 4 3 2 1 0 High S W Clear To interrupt block DACIE 4 DAC Offset Controller OFSEN OFSDIR OFS 3 0 4 SPI2DR 8 BIT SPI3DR 8 BIT D AC Interface Controller DACIFEN MDSEL SPISEL 12 CMD 3 0...

Page 299: ...r DACBRL 40C4H XSFR R 00H D A Converter Buffer Low Register DAOFSCR 40C8H XSFR R W 00H D A Converter Offset Control Register DACIFCR 40C9H XSFR R W 00H D AC Interface Control Register DACIFCMD 40CAH X...

Page 300: ...CDR 15 0 is a binary format DACBRH D A Converter Buffer High Register 40C5H XSFR 7 6 5 4 3 2 1 0 DACBR15 DACBR14 DACBR13 DACBR12 DACBR11 DACBR10 DACBR9 DACBR8 R R R R R R R R Initial value 00H DACBR 1...

Page 301: ...t 1 Automatically D AC data increment from DACDR value to 800xH when DACEN bit is changed to 1b Automatically D AC data decrement from DACDR value to 000xH when DACEN bit is changed to 0b NOTE 1 It do...

Page 302: ...1 0dB 0 1 1 0 6dB 0 1 1 1 12dB 1 0 0 0 18dB 1 0 0 1 24dB 1 0 1 0 30dB Other Values Not available DAOFSCR D A Converter Offset Control Register 40C8H XSFR 7 6 5 4 3 2 1 0 OFSEN OFSDIR OFS3 OFS2 OFS1 O...

Page 303: ...IFEN bit is set to 1b and the MDSEL bit is set to 1b 0 Not effect 1 LDACB2 function instead of MISO2 NOTE 1 Refer to the P3FSRL register for P3FSRL 7 6 bits CSB3FS CSB3 Function Selection Bit This bit...

Page 304: ...frequency of COM signal scanning of each segment output A RESET clears the LCD control register LCDCRH LCDCRL and LCDCCR values to logic 0 The LCD display can continue operating during IDLE and STOP m...

Page 305: ...Therefore display patterns can be changed by only overwriting the contents of the display external data area with a program Figure 11 89 shows the correspondence between the display external data are...

Page 306: ...Frame VDD VSS 0 1 COM1 SEG2 COM0 SEG1 COM0 VSS VLC0 VLC1 VLC2 VLC3 COM0 COM1 SEG1 SEG2 SEG4 0 1 SEG3 SEG1 VSS VLC0 VLC1 VLC2 VLC3 VSS VLC0 VLC1 VLC2 VLC3 VLC1 VLC2 VLC3 VLC0 VSS VLC0 VLC1 VLC2 VLC3 VS...

Page 307: ...rame VDD VSS 0 1 COM1 SEG3 COM0 SEG2 COM0 VLC2 VLC3 VLC0 VLC1 SEG2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 0 1 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3...

Page 308: ...me VDD VSS 0 1 COM1 SEG4 COM0 SEG3 COM0 VLC2 VLC3 VLC0 VLC1 SEG3 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 2 VSS VLC2 VLC3 VLC0 VLC1 VSS COM2 VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC1 VSS VLC2 VLC3 VLC0 VLC...

Page 309: ...1 0 S E G 1 1 1 Frame VDD VSS 0 COM1 SEG8 COM0 SEG7 COM0 VLC2 VLC0 VLC1 SEG7 VSS COM2 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VLC0 VLC1 VSS VLC3 VLC2 VL...

Page 310: ...R R VLC 0 VLC 1 VLC 2 VLC 3 VLCD 1 4 BIAS VLC 0 VLC 1 VLC 2 VLC 3 VSS R R VLC 0 VLC 1 VLC 2 VLC 3 VLCD 1 2 Bias VLC 0 VLC 1 VLC 2 VLC 3 LCTEN DISP VSS R VLC 0 VLC 1 VLC 2 VLC 3 VLCD 1 3 BIAS VLC 0 VL...

Page 311: ...ted as VLC0 VLC1 and VLC2 functions The P70 VLC3 pin can be used for normal I O When it is 1 4 bias the P73 VLC0 P72 VLC1 P71 VLC2 and P70 VLC3 pins should be selected as VLC0 VLC1 VLC2 and VLC3 funct...

Page 312: ...LC2 VLC3 R R R R VLCD External Resistor Bias VLC0 VLC1 VLC2 VLC3 VSS R LCTEN DISP Contrast Controller Off Off LCTEN DISP Contrast Controller Off Off VSS R R R VLC0 VLC1 VLC 2 VLC3 VLCD Internal Resist...

Page 313: ...313 MC97F60128 ABOV Semiconductor Co Ltd 11 16 5 LCD AUTOMATIC BIAS CONTROL Bias Mode A Bias Mode B Bias Mode A Bias Mode B Figure 11 97 Bias Mode A and Bias Mode B...

Page 314: ...ltage Bias COM Port Driver VLC2 VLC1 VLC0 VLC3 LCDCCR LCDBCR SEG Port Driver Figure 11 98 LCD Circuit Block Diagram NOTE 1 The clock and duty for LCD driver is automatically initialized by hardware wh...

Page 315: ...d LCD driver contrast control register LCDCCR 11 16 9 Register Description for LCD Driver LCDCRH LCD Driver Control High Register 400BH XSFR 7 6 5 4 3 2 1 0 IRSEL1 IRSEL0 LCDDR DISP R W R W R W R W In...

Page 316: ...scription 0 0 0 1 8Duty 1 4Bias 0 0 1 1 6Duty 1 4Bias 0 1 0 1 5Duty 1 3Bias 0 1 1 1 4Duty 1 3Bias 1 0 0 1 3Duty 1 3Bias 1 0 1 1 3Duty 1 2Bias 1 1 0 1 2Duty 1 2Bias 1 1 1 Not available LCLK 1 0 LCD Clo...

Page 317: ...LCDCC2 LCDCC1 LCDCC0 Description 0 0 0 0 16 31 x VDD 0 0 0 1 16 30 x VDD 0 0 1 0 16 29 x VDD 0 0 1 1 16 28 x VDD 0 1 0 0 16 27 x VDD 0 1 0 1 16 26 x VDD 0 1 1 0 16 25 x VDD 0 1 1 1 16 24 x VDD 1 0 0...

Page 318: ...64 LCD COM Period 1 0 0 5 64 59 64 LCD COM Period 1 0 1 6 64 58 64 LCD COM Period 1 1 0 7 64 57 64 LCD COM Period 1 1 1 8 64 56 64 LCD COM Period BMODEB 1 0 Select Bias Mode B Resistor Refer to the Fi...

Page 319: ...inform register 1 2 VPINF1 2 11 17 2 Function Description The bundle size and sampling frequency should be set to decode voice prompt data The sampling frequency is an interval to play It can be adjus...

Page 320: ...ck fx Sampling frequency fs Divider 1 Where the divider is one of 2 4 8 and 16 X 1 2 4 3 4 1 2 4 0 Decoder clock Decoder Counter DECDR 7 0 Decoder Result Output Data Match 0 Clear and Start 3 3 8 0 2...

Page 321: ...al flash VCC 3V Set the SPI2_3V bit the P3FSRH 7 to 1b for reading 3V output of the serial flash Set the nCS pin of the serial flash to low level for the serial flash selection Write read instruction...

Page 322: ...he buffer register of D A converter 6 Write the DECCR register to 000011xxb Disable decoder FIFO empty and match interrupts Disable decoder block and initialize decoder block and enable decoder counti...

Page 323: ...UMY1 DUMY2 DUMYn X MISO DATA0 DATA7 DATA0 CSB SFRDST This bit is automatically cleared to 0 after being exection FIFO DFIFOR DFIFOR DFIFOR FIFO Empty Signal FIFO Empty Interrupt Voice Prompt Size Regi...

Page 324: ...rompt Size Decrement by 1 VPSIZE1 2 3 Registers VPSDEC If match 0 Comparator 0x000000 2 ATRIGS 1 0 2 bits up counter VPEDIE To interrupt block VPEDIFR OVF Internal Flag If 1 Clear signal M U X SPICSS...

Page 325: ...ADDR2 40B9H XSFR R W 00H Voice Prompt Address Register 2 VPADDR3 40BAH XSFR R W 00H Voice Prompt Address Register 3 VPSIZE1 40BBH XSFR R W 00H Voice Prompt Size Register 1 VPSIZE2 40BCH XSFR R W 00H V...

Page 326: ...polation data get out between every the voice data ex data1 data1 data2 2 data2 data2 data3 2 DBDLR FADPCM Decoder Bundle Register 40B3H XSFR 7 6 5 4 3 2 1 0 DBDLR7 DBDLR6 DBDLR5 DBDLR4 DBDLR3 DBDLR2...

Page 327: ...W R W Initial value 00H VPAR 15 8 Voice Prompt Address Mid byte VPADDR3 Voice Prompt Address Register 3 40BAH XSFR 7 6 5 4 3 2 1 0 VPAR7 VPAR6 VPAR5 VPAR4 VPAR3 VPAR2 VPAR1 VPAR0 R W R W R W R W R W R...

Page 328: ...t Inform High byte VPINF2 Voice Prompt Inform Register 2 40BFH XSFR 7 6 5 4 3 2 1 0 VPINF7 VPINF6 VPINF5 VPINF4 VPINF3 VPINF2 VPINF1 VPINF0 R W R W R W R W R W R W R W R W Initial value 00H VPINF 7 0...

Page 329: ...0 Disable 1 Enable DFFF Decoder FIFO Full Flag 0 Not decoder FIFO full 1 Decoder FIFO full DECEN Decoder Block Enable 0 Disable decoder block 1 Enable decoder block DIVS Decoder Initial Value Setting...

Page 330: ...SPI2 to interface 1 Select SPI3 to interface VPSDEC Voice Prompt Size Register Decrement Enable 0 No effect 1 Voice prompt size register is decreased by 1 every interface DTRS Enable Data Transfer fro...

Page 331: ...prompt end interrupt generation VPTBLIFR When voice prompt table data receive end interrupt occurs this bit becomes 1 The flag is cleared only by writing a 0 to the bit So the flag should be cleared b...

Page 332: ...WM Operates Continuously Stop ADC Operates Continuously Stop DAC Operates Continuously Retain output level BUZ Operates Continuously Stop SPI2 3 Operates Continuously Only operate with external clock...

Page 333: ...s and peripherals are operated normally but CPU stop It is released by reset or interrupt To be released by interrupt interrupt should be enabled before IDLE mode If using reset because the device bec...

Page 334: ...h the sub clock The source for exit from STOP mode is hardware reset and interrupts The reset re defines all the control registers When exit from STOP mode enough oscillation stabilization time is req...

Page 335: ...e STOP mode is released by the interrupt which each interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP mode is released...

Page 336: ...87H 7 6 5 4 3 2 1 0 PCON7 PCON3 PCON2 PCON1 PCON0 R W R W R W R W R W Initial value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation NOTE 1 To enter I...

Page 337: ...et Source The MC97F60128 has five types of reset sources The following is the reset sources External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 Low Voltage Reset In the case o...

Page 338: ...celler The Figure 13 2 is the noise canceller diagram for noise cancellation of RESET It has the noise cancellation value of about 2us VDD 5V to the low input of system reset Figure 13 2 Reset noise c...

Page 339: ...RESET function instead of the RESET IC or the RESET circuits Figure 13 3 Fast VDD Rising Time Figure 13 4 Internal RESET Release Timing On Power Up VDD nPOR Internal Signal Internal RESETB Oscillatio...

Page 340: ...ternal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8 INT OSC 8MHz RESET_SYSB Config Read 1us X 256 X 28h about 10ms 1us X 4096 X 4h about 16ms 00 01 02 03 00 27 28 F1 Counting...

Page 341: ...r Config read Slew Rate 0 05V ms Config read point about 1 5V 1 6V Config Value is determined by Writing Option Rising section to Reset Release Level 16ms point after POR or Ext_reset release Reset Re...

Page 342: ...te the internal RESET becomes 1 The Reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 13 7 Timing Diagram after RESET F...

Page 343: ...44V 2 59V 2 75V 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption the LVREN bit is set to...

Page 344: ...V 2 75V LVI Circuit LVILS 3 0 2 93V 3 14V 3 38V 3 67V 4 00V 4 40V 2 10V 2 20V 2 32V 2 00V 4 Figure 13 12 LVI Diagram VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8MHz 8...

Page 345: ...Register RSTFR E8H R W 80H Reset Flag Register LVRCR D8H R W 00H Low Voltage Reset Control Register Table 13 3 Reset Operation Register Map 13 10 Reset Operation Register Description The reset contro...

Page 346: ...VRF Low Voltage Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection FPRIRF Flash ROM Parity Fail Reset flag bit This bit is set to 1 by a reset of...

Page 347: ...it is 0 the LVREN bit is not effect by stop mode to release LVRVS 3 0 LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 0 0 0 0 1 60V 0 0 0 1 2 00V 0 0 1 0 2 10V 0 0 1 1 2 20V 0 1 0 0 2 32V 0...

Page 348: ...H LVIF Low Voltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVILS 3 0 LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0 Description 0 0 0 0 2 00V 0 0 0 1 2...

Page 349: ...On chip debug system OCD2 of MC97F60128 can be used for programming the non volatile memories and on chip debugging Detail descriptions for programming via the OCD2 interface can be found in the follo...

Page 350: ...uding Break Instruction Single Step Break Program Memory Break Points on Single Address Programming of Flash EEPROM Fuses and Lock Bits through the two wire Interface On chip Debugging Supported by OC...

Page 351: ...bit as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When acknowledge...

Page 352: ...3 Data Transfer on the Twin Bus 14 2 2 2 Bit Transfer Figure 14 4 Bit Transfer on the Serial Bus data line stable data valid except Start and Stop change of data allowed DSDA DSCL St Sp START STOP DS...

Page 353: ...ocedure Start wait start HIGH Host PC DSCL OUT Target Device DSCL OUT DSCL wait HIGH Maximum 5 TSCLK Internal Operation Acknowledge bit transmission minimum 1 TSCLK for next byte transmission Acknowle...

Page 354: ...of Transmission 14 2 4 Circuit DSCL OUT DSDA OUT DSDA IN DSCL Debugger Serial Clock Line DSDA Debugger Serial Data Line DSDA OUT DSDA IN Host Machine Master Target Device Slave VDD Current source for...

Page 355: ...h memory can be read by MOVC instruction and it can be programmed in OCD serial ISP mode or user program mode Flash Size 128kbytes Single power supply program and erase Command interface for fast prog...

Page 356: ...FH Sector 1020 Sector 2 00100H 000FFH 00080H Sector 1 00080H 0007FH 00000H Sector 0 00000H 00100H 8000H Flash Page Buffer External Data Memory 128bytes 807FH ROM Address Accessed by MOVX instruction o...

Page 357: ...lash Identification Register FMCR FEH R W 00H Flash Mode Control Register Table 15 1 Flash Memory Register Map 15 1 4 Register Description for Flash Memory Control and Status Flash control register co...

Page 358: ...l value 00H FSADRM 7 0 Flash Sector Address Middle FSADRL Flash Sector Address Low Register FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R W R W R W R W R W R W...

Page 359: ...nterrupt is on disable state regardless of the IE 7 EA bit FMCR2 FMCR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value Clear all 128bytes to 0 0 1 0...

Page 360: ...tection area at the configure option 2 if it is needed If the protection area isn t enabled PAEN 1 this area can be used as a normal program memory The size of protection area can be varied by setting...

Page 361: ...is instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address is 8000H MOV DPL 0 Pgbuf_clr MOVX D...

Page 362: ...be needed NOP Dummy instruction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 0 MOV R0 SectorSize Sector size of Device MOV DPH 0x80 Page Buffer Address i...

Page 363: ...ion must be needed NOP Dummy instruction This instruction must be needed NOP Dummy instruction This instruction must be needed MOV A 5 MOV DPH 0x80 MOV DPL 0 MOVX DPTR A Write data to page buffer MOV...

Page 364: ...rase MOV A ID_DATA_3 CJNE A UserID3 No_WriteErase MOV FMCR 0x 0x03 if write 0x02 if erase RET No_WriteErase MOV FIDR 00H MOV UserID1 00H MOV UserID2 00H MOV UserID3 00H MOV Flash_flag 00H RET If code...

Page 365: ...L Work2 CALL ID_write CALL Work3 CALL Flash_erase CALL Flash_write ID_wire MOV A 38H CJNE A Flash_flag1 No_write_ID MOV A 75H CJNE A Flash_flag2 No_write_ID MOV UserID1 ID_DATA_1 Write Uiser ID1 MOV A...

Page 366: ...ase for flash memory to be erased by malfunction noise and power off Figure 15 2 Flow of Protection for Invalid Erase Write Start Work1 Set Flags Write UserID1 2 3 Clear the Flag Clear UserID1 2 3 Wri...

Page 367: ...program mode 1 Set flash identification register FIDR 2 Check the UserID for to prevent the invalid work Note 3 Set flash mode control register FMCR NOTE Please refer to the chapter Protection for Inv...

Page 368: ...VAPEN Vector Area 00H FFH Protection Enable Disable 0 Disable Protection Erasable by instruction 1 Enable Protection Not erasable by instruction CONFIGURE OPTION 2 ROM Address 003EH 7 6 5 4 3 2 1 0 PA...

Page 369: ...t byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB A d...

Page 370: ...1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive OR d...

Page 371: ...A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 83 MOVX A Ri Move external data A8 to A 1 2 E2 E3 MOVX A DPTR Move external data A16 to A 1 2 E0 MOVX Ri...

Page 372: ...mpare register immediate jne relative 3 2 B8 BF CJNE Ri d rel Compare indirect immediate jne relative 3 2 B6 B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 DF DJNZ dir rel Decrement direct byte...

Page 373: ...the flags in program and check the flags in main loop at the end When the Flash Erase Write is executed check the flags If not matched do not execute Check the range of Flash Sector Address If the fla...

Page 374: ...Write Flash Set User_ID1 Working Check User_ID1 Set User_ID2 Working Check User_ID2 Set User_ID3 Working Yes Yes Yes No No No Write Flash Clear User_ID1 2 3 Clear FIDR Clear FMCR Set FSADRH M L to Dum...

Page 375: ...e Write in flash Set to Dummy address after Erase Write Even if invalid work occurred it will be Erase Write in Dummy address in flash Check Flags If every flag User_ID1 2 3 LVI Flash Address Min Max...

Page 376: ...e Indicator Characteristics 33 7 7 Phase Locked Loop Characteristics 33 7 8 Internal RC Oscillator Characteristics 34 7 9 Internal Watch Dog Timer RC Oscillator Characteristics 34 7 10 LCD Voltage Cha...

Page 377: ...2 Register description for P4 93 9 8 P5 Port 97 9 8 1 P5 Port Description 97 9 8 2 Register description for P5 97 9 9 P6 Port 100 9 9 1 P6 Port Description 100 9 9 2 Register description for P6 100 9...

Page 378: ...imer Register Description 146 11 2 5 Register Description for Basic Interval Timer 146 11 3 Watch Dog Timer 148 11 3 1 Overview 148 11 3 2 WDT Interrupt Timing Waveform 148 11 3 3 Block Diagram 149 11...

Page 379: ...rview 220 11 9 3 Register Map 221 11 9 4 Buzzer Driver Register Description 221 11 9 5 Register Description for Buzzer Driver 221 11 10 SPI 2 222 11 10 1 Overview 222 11 10 2 Block Diagram 222 11 10 3...

Page 380: ...0 1 SPI Clock Formats and Timing 262 11 13 22 USI0 1 SPI Block Diagram 265 11 13 23 USI0 1 I2C Mode 266 11 13 24 USI0 1 I2C Bit Transfer 266 11 13 25 USI0 1 I2C Start Repeated Start Stop 267 11 13 26...

Page 381: ...eration 332 12 1 Overview 332 12 2 Peripheral Operation in IDLE STOP Mode 332 12 3 IDLE Mode 333 12 4 STOP Mode 334 12 5 Release Operation of STOP Mode 335 12 6 Register Map 336 12 7 Power Down Operat...

Page 382: ...erial In System Program ISP Mode 360 15 1 7 Protection Area User program mode 360 15 1 8 Erase Mode 361 15 1 9 Write Mode 362 15 1 10 Protection for Invalid Erase Write 364 15 1 10 1 Flow of Protectio...

Reviews:

No comments