Abov MC97F60128, User Manual, Page: 331 / 382

331
MC97F60128 ABOV Semiconductor Co., Ltd.
FAFLAG (FADPCM Interrupt Flag Register) : 40B6H (XSFR)
7 6 5 4 3 2 1 0
SFSTOP
– – –
VPEDIFR VPTBLIFR DFEIFR DMIFR
R/W
– – –
R/W R/W R/W R/W
Initial value : 00H
SFSTOP Stop the Serial Flash Interface for reading voice data
0 No effect
1 Stop with a serial flash interface (When write, automatically cleared
‘0’
after being execution)
NOTE)
1.
It should not be restarted an interface by the SFRDST bit set
to
‘1’ until the end of the current byte interface with SPI2 or
SPI3
VPEDIFR When voice prompt end interrupt occurs, this bit becomes
‘1’. The flag is cleared only
by writing a
‘0’ to the bit. So, the flag should be cleared by software. Write ‘1’ has no
effect.
0 Voice prompt end interrupt no generation
1 Voice prompt end interrupt generation
VPTBLIFR When voice prompt table data receive end interrupt occurs, this bit becomes
‘1’. The
flag is cleared only by writing a
‘0’ to the bit. So, the flag should be cleared by software.
Write
‘1’ has no effect.
0 Voice prompt table data receive end interrupt no generation
1 Voice prompt table data receive end interrupt generation
DFEIFR When FADPCM decoder FIFO empty interrupt occurs, this bit becomes
‘1’. The flag is
cleared only by writing a
‘0’ to the bit. So, the flag should be cleared by software. Write
‘1’ has no effect.
0 FADPCM decoder FIFO empty interrupt no generation
1 FADPCM decoder FIFO empty interrupt generation
DMIFR When FADPCM decoder match interrupt occurs, this bit becomes
‘1’. The flag is
cleared only by writing a
‘0’ to the bit. So, the flag should be cleared by software. Write
‘1’ has no effect.
0 FADPCM decoder match interrupt no generation
1 FADPCM decoder match interrupt generation