235
MC97F60128
ABOV Semiconductor Co., Ltd.
SPI3CR (SPI 3 Control Register) : 400DH (XSFR)
7
6
5
4
3
2
1
0
SPI3EN
FLSB3
SPI3MS
CPOL3
CPHA3
SPI3DSCR
SPI3SCR1
SPI3SCR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
SPI3EN
This bit controls the SPI 3 operation
0
Disable SPI 3 operation
1
Enable SPI 3 operation
FLSB3
This bit selects the data transmission sequence
0
MSB first
1
LSB first
SPI3MS
This bit selects whether Master or Slave mode
0
Slave mode
1
Master mode
CPOL3
CPHA3
This two bits control the serial clock (SCK3) mode.
Clock polarity (CPOL3) bit determine SCK3
’s value at idle mode.
Clock phase (CPHA3) bit determine if data are sampled on the leading or trailing edge
of SCK3.
CPOL3 CPHA3
Leading edge
Trailing edge
0
0
Sample (Rising)
Setup (Falling)
0
1
Setup (Rising)
Sample (Falling)
1
0
Sample (Falling)
Setup (Rising)
1
1
Setup (Falling)
Sample (Rising)
SPI3DSCR
SPI3SCR [1:0]
These three bits select the SCK3 rate of the device configured as a master. When
DSCR bit is written one, SCK3 will be doubled in master mode.
SPI3DSCR SPI3SCR 1 SPI3SCR 0 SCK3 frequency
0
0
0
fx/4
0
0
1
fx/16
0
1
0
fx/64
0
1
1
fx/128
1
0
0
fx/2
1
0
1
fx/8
1
1
0
fx/32
1
1
1
fx/64
Summary of Contents for MC97F60128
Page 17: ...17 MC97F60128 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 100 pin LQFP 1414 Package...
Page 18: ...18 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 2 80 Pin LQFP 1212 Package...
Page 19: ...19 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 3 80 Pin LQFP 1414 Package...
Page 20: ...20 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 4 64 Pin LQFP 1414 Package...