Abov MC97F60128, User Manual, Page: 303 / 382

303
MC97F60128 ABOV Semiconductor Co., Ltd.
DACIFCR (D/AC Interface Control Register) : 40C9H (XSFR)
7 6 5 4 3 2 1 0
DACIFEN
–
LDACB3FS LDACB2FS CSB3FS CSB2FS SPISEL MDSEL
R/W
–
R/W R/W R/W R/W R/W R/W
Initial value : 00H
PGS[3:0] D/AC Interface Enable Bit
0 Disable
1 Enable
LDACB3FS LDACB3 Function Selection Bit. This bit is effective only when the P3FSRH[6:5] bits are
set to
“00b”, the SPISEL bit is set to “1b”, the DACIFEN bit is set to “1b” and the MDSEL
bit is set to
“1b”.
0 Not effect
1 LDACB3 function instead of MISO3
NOTE)
1.
Refer to the P3FSRH register for P3FSRH[6:5] bits.
LDACB2FS LDACB2 Function Selection Bit. This bit is effective only when the P3FSRL[7:6] bits are
set to
“00b”, the SPISEL bit is set to “0b”, the DACIFEN bit is set to “1b” and the MDSEL
bit is set to
“1b”.
0 Not effect
1 LDACB2 function instead of MISO2
NOTE)
1.
Refer to the P3FSRL register for P3FSRL[7:6] bits.
CSB3FS CSB3 Function Selection Bit. This bit is effective only when the P2FSRL4 bit is set to
“0b”, the SPISEL bit is set to “1b” and the DACIFEN bit is set to “1b”.
0 Not effect
1 CSB3 function instead of SS3
NOTE)
1.
Refer to the P2FSRL register for P2FSRL4 bit.
CSB2FS CSB2 Function Selection Bit. This bit is effective only when the P3FSRH4 bit is set to
“0b”, the SPISEL bit is set to “0b” and the DACIFEN bit is set to “1b”.
0 Not effect
1 CSB2 function instead of SS2
NOTE)
1.
Refer to the P3FSRH register for P3FSRH4 bit.
SPISEL SPI Block Selection to transfer data to an external D/AC
0 Select SPI2
1 Select SPI3
MDSEL Mode Selection Bit
0 Mode 0
1 Mode 1
NOTE)
1. This D/AC interface block doesn
’t work when DACRLDS bits of the DACCR register are set to
“00b”.