191
MC97F60128
ABOV Semiconductor Co., Ltd.
PWM output Delay
If using the T8DLYA, T8DLYB, T8DLYC register, it can delay PWM output based on the rising edge. At that time, it
does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA
setting to ‘0’, the delay is
applied to the falling edge. In POLAA/BA/CA
setting to ‘1’, the delay is applied to the rising edge. It can produce a pair
of Non-overlapping clock. The each channel is able to have 4-bit delay. As it can select the clock up to 1/8 divided
clock using NOPS[1:0] the delay of its maximum 128 timer clock cycle is produced.
Summary of Contents for MC97F60128
Page 17: ...17 MC97F60128 ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 100 pin LQFP 1414 Package...
Page 18: ...18 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 2 80 Pin LQFP 1212 Package...
Page 19: ...19 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 3 80 Pin LQFP 1414 Package...
Page 20: ...20 MC97F60128 ABOV Semiconductor Co Ltd Figure 4 4 64 Pin LQFP 1414 Package...