Abov MC97F60128, User Manual, Page: 62 / 382

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MC97F60128 ABOV Semiconductor Co., Ltd.
Address Function Symbol R/W
@Reset
7 6 5 4 3 2 1 0
C0H P7 Data Register P7 R/W 0 0 0 0 0 0 0 0
C1H P6 Direction Register P6IO R/W
– –
0 0 0 0 0 0
C2H External Interrupt Polarity 0 Low Register EIPOL0L R/W 0 0 0 0 0 0 0 0
C3H External Interrupt Polarity 0 High Register EIPOL0H R/W 0 0 0 0 0 0 0 0
C4H External Interrupt Polarity 2 Low Register EIPOL2L R/W 0 0 0 0 0 0 0 0
C5H External Interrupt Polarity 2 High Register EIPOL2H R/W 0 0 0 0 0 0 0 0
C6H External Interrupt Polarity 3 Low Register EIPOL3L R/W 0 0 0 0 0 0 0 0
C7H External Interrupt Polarity 3 High Register EIPOL3H R/W
– – – – – –
0 0
C8H Oscillator Control Register OSCCR R/W
– –
0 0 1 0 0 0
C9H P7 Direction Register P7IO R/W 0 0 0 0 0 0 0 0
CAH External Interrupt Polarity 4 Low Register EIPOL4L R/W 0 0 0 0 0 0 0 0
CBH External Interrupt Polarity 4 High Register EIPOL4H R/W
– – – – – –
0 0
CCH P0 Debounce Enable Register P0DB R/W 0 0 0 0 0 0 0 0
CDH P1 Debounce Enable Register P1DB R/W 0 0 0 0 0 0 0 0
CEH P46 Debounce Enable Register P46DB R/W
– – –
0 0 0 0 0
CFH P9 Debounce Enable Register P9DB R/W
– – –
0 0 0 0 0
D0H Program Status Word Register PSW R/W 0 0 0 0 0 0 0 0
D1H P8 Direction Register P8IO R/W 0 0 0 0 0 0 0 0
D2H Timer 0 Control Register T0CR R/W 0
–
0 0 0 0 0 0
D3H Timer 0 Counter Register T0CNT R 0 0 0 0 0 0 0 0
D4H Timer 0 Data Register T0DR R/W 1 1 1 1 1 1 1 1
D4H Timer 0 Capture Data Register T0CDR R 0 0 0 0 0 0 0 0
D5H Timer Interrupt Flag Register TIFLAG R/W
– –
0 0 0 0 0 0
D6H Phase Locked Loop Control Register PLLCR R/W
– –
0 0 0 0 0 0
D7H PA Debounce Enable Register PADB R/W
– – –
0 0 0 0 0
D8H Low Voltage Reset Control Register LVRCR R/W 0
– –
0 0 0 0 0
D9H P9 Direction Register P9IO R/W
– – –
0 0 0 0 0
DAH Timer 1 Control Register T1CR R/W 0
–
0 0 0 0 0 0
DBH Timer 1 Counter Register T1CNT R 0 0 0 0 0 0 0 0
DCH Timer 1 Data Register T1DR R/W 1 1 1 1 1 1 1 1
DCH Timer 1 Capture Data Register T1CDR R 0 0 0 0 0 0 0 0
DDH Timer 2 Control Register T2CR R/W 0
–
0 0 0 0 0 0
DEH Timer 2 Counter Register T2CNT R 0 0 0 0 0 0 0 0
DFH Timer 2 Data Register T2DR R/W 1 1 1 1 1 1 1 1
DFH Timer 2Capture Data Register T2CDR R 0 0 0 0 0 0 0 0
Table 8-5 Table 8.3 SFR Map (Continued)