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Abov A96G166 User Manual Download Page 88

11. Timer 0/1/2 

 

A96G166/A96A166/A96S166 User’s manual

 

 

88 

11.1.3

 

8-bit capture mode 

Timer  0  capture  mode  is  set  by  configuring  T0MS[1:0]  as  ‘1x’.  Clock  source  can  use  the 

internal/external clock.  Basically, it has the same function as the 8-bit timer/counter mode has, and 
the  interrupt  occurs  when  T0CNT  equals  to  T0DR.  T0CNTvalue  is  automatically  cleared  by  match 
signal and it can be also cleared by software (T0CC). 

This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider 
than the maximum period of timer. 

The capture result is loaded into T0CDR. In the timer 0 capture mode, timer 0 output (T0O) waveform 
is not available. 

According to  EIPOL1 registers setting, the external interrupt  EINT10 function is  chosen. Of course, 
the EINT10 pin must be set to an input port. 

T0CDR and T0DR are in the same address. In the capture mode, reading operation readsT0CDR, not 
T0DR and writing operation will update T0DR. 

 

P

r

e
s
c
a

l

e

r

fx

M

U
X

fx/2

T0CNT(8Bit)

EC0

fx/4

fx/8

fx/32

fx/128

fx/512

fx/2048

3

T0CK[2:0]

T0EN

8-bit Timer 0 Counter

T0DR(8Bit)

Comparator

T0IFR

8-bit Timer 0 Data  Registe r

INT_ACK

Clear

Match

MUX

T0CDR(8Bit)

Clear

FLAG10

(EIFLAG1.4)

2

T0MS[1:0]

2

T0MS[1:0]

INT_ACK

Clear

To in terru pt
block

To in terru pt
block

T0EN

-

T0MS1

T0MS0

T0CK2

T0CK1

T0CK0

T0CC

T0CR

1

-

1

x

x

x

x

x

ADDRES S : B2H
INITIAL VALUE: 0000_0000B

Clear

EINT10

EIPOL1[1:0]

2

Match  signa l

T0CC

 

 

Figure 35. 8-bit Capture Mode for Timer 0 

 

 

Summary of Contents for A96G166

Page 1: ...ngs to offer highly flexible and cost effective solutions 16Kbytes of FLASH 256bytes of IRAM 512bytes of XRAM general purpose I O basic interval timer watchdog timer 8 16 bit timer counter 16 bit PPG...

Page 2: ...register PxPU 39 5 1 4 Open drain Selection Register PxOD 39 5 1 5 De bounce Enable Register PxDB 39 5 1 6 Port Function Selection Register PxFSR 39 5 1 7 Register Map 40 5 2 P0 port 41 5 2 1 P0 port...

Page 3: ...ng window open period of watchdog timer 77 9 2 WDT block diagram 78 9 3 Register map 78 9 4 Register description 79 10 Watch timer 81 10 1 WT block diagram 81 10 2 Register map 82 10 3 Watch timer reg...

Page 4: ...4 8 Register Map 133 14 9 I2C register description 134 15 USART 0 1 138 15 1 Block diagram 139 15 2 Clock generation 140 15 3 External clock XCK 141 15 4 Synchronous mode operation 141 15 5 Data forma...

Page 5: ...1 Flash operation 190 19 4 Mode entrance method of ISP mode 195 19 4 1 Mode entrance method for ISP 195 19 5 Security 196 19 6 Configure option 197 19 7 Password function 199 20 Electrical characteri...

Page 6: ...0 SOP package information 224 21 4 24 QFN package information 225 21 5 28 SOP package information 226 21 6 32 LQFP package information 227 22 Development tools 228 22 1 Compiler 228 22 2 OCD On chip d...

Page 7: ...ntry Address of ISR 61 Figure 24 Saving Restore Process Diagram and Sample Source 61 Figure 25 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction 62 Figure 26 Clock Generator Block...

Page 8: ...n 0 1 139 Figure 71 Clock Generation Block Diagram 140 Figure 72 Synchronous Mode XCKn Timing n 0 1 141 Figure 73 A Frame Format 142 Figure 74 Start Bit Sampling 146 Figure 75 Sampling of Data and Pa...

Page 9: ...18 Clock Timing Measurement at SXIN 217 Figure 119 Operating Voltage Range 218 Figure 120 Recommended Voltage Range 218 Figure 121 RUN IDD1 Current 219 Figure 122 IDLE IDD2 Current 220 Figure 123 SUB...

Page 10: ...Mode 84 Table 16 Timer 0 Register Map 90 Table 17 TIMER 1 Operating Modes 92 Table 18 TIMER 1 Register Map 102 Table 19 TIMER 2 Operating Modes 105 Table 20 TIMER 2 Register Map 112 Table 21 Buzzer F...

Page 11: ...C Characteristics 206 Table 53 AC Characteristics 207 Table 54 USART Timing Characteristics in SYNC or SPI Mode Operations 208 Table 55 SPI Characteristics 211 Table 56 I2C Characteristics 212 Table 5...

Page 12: ...ipheral Counts Peripherals Description Core CPU 8 bit CISC core M8051 2 clocks per cycle Interrupt Up to 21 peripheral interrupts supported EINT0 to 4 EINT5 EINT6 EINT7 to A EINT10 EINT11 EINT12 7 Tim...

Page 13: ...Watchdog timer WDT 8 bit x 1 ch 8 bit x 1 ch T0 16 bit x 2 ch T1 T2 Communication function USART UART SPI 8 bit USART x 2 ch or 8 bit SPI x 2 ch Receiver timer out RTO 0 error baud rate I2C 8 bit I2C...

Page 14: ...indicator Power down mode Clock generator 32MHz Internal RC OSC 128kHz Internal RC OSC 12MHz Crystal OSC 32 768kHz Crystal OSC UART 2 channels 8 bit SPI 2 channels 8 bit I2C 1 channels 8 bit CORE M805...

Page 15: ...6 XIN P26 EC0 P25 SCL RXD1 P24 SDA TXD1 P22 EINT9 XCK1 LED6 P00 AN0 DSDA P01 AN1 DSCL P06 AN6 EINT4 T2O PWM2O P12 AN9 EINT11 T1O PWM1O LED0 P13 AN10 EINT12 T2O PWM2O LED1 P14 AN11 RXD0 P15 AN12 TXD0 N...

Page 16: ...as a push pull output or an input with pull up resistor by software control when the 20 pin package is used Figure 3 A96G166 20TSSOP 20SOP Pin Assignment A96A166FD 20SOP 1 4 3 2 VSS 6 5 VDD 7 10 9 8 2...

Page 17: ...1 LED6 P00 AN0 DSDA P01 AN1 DSCL P02 AN2 EINT0 P03 AN3 EINT1 T1O PWM1O P10 AN7 EINT5 PWM1OB P11 AN8 EINT6 EC1 BUZO P12 AN9 EINT11 T1O PWM1O LED0 P13 AN10 EINT12 T2O PWM2O LED1 P21 EINT8 SS1 LED5 NOTES...

Page 18: ...B P11 AN8 EINT6 EC1 BUZO VS S VDD P37 XO UT P30 EC2 TXD1 SDA P23 EINTA LED7 P16 AN13 XCK0 LED2 P15 AN12 TXD0 P12 AN9 EINT11 T1O PWM1O LED0 P13 AN10 EINT12 T2O PWM2O LED1 P34 SXIN P33 SXOUT P00 AN0 DSD...

Page 19: ...EINT0 P16 AN13 XCK0 LED2 P15 AN12 TXD0 P11 AN8 EINT6 EC1 BUZO P10 AN7 EINT5 PWM1OB P13 AN10 EINT12 T2O PWM2O LED1 P12 AN9 EINT11 T1O PWM1O LED0 P14 AN11 RXD0 NOTES 1 The programmer E PGM E Gang4 6 use...

Page 20: ...ut output AN3 IA ADC input ch 3 EINT1 I External interrupt input ch 1 T1O O Timer 1 interval output PWM1O O Timer 1 PWM output 24 P04 IOUS Port 0 bit 4 Input output AN4 IA ADC input ch 4 EINT2 I Exter...

Page 21: ...16 18 11 9 P15 IOUS Port 1 bit 5 Input output AN12 IA ADC input ch 12 TXD0 O USART0 data transmit 15 17 10 P16 IOUS Port 1 bit 6 Input output AN13 IA ADC input ch 13 LED2 O High sink current ports XCK...

Page 22: ...put SXOUT O Sub Oscillator Output 2 5 2 P34 IOUS Port 3 bit 4 Input output SXIN I Sub Oscillator Input 1 4 1 4 4 4 P35 IOUS Port 3 bit 5 Input output EINT10 I External interrupt input ch 10 T0O O Time...

Page 23: ...ith internal pull up resistor only during the reset or power on reset 9 The P36 XIN P37 XOUT P33 SXOUT and P34 SXIN pins are configured as a function pin by software control 10 1 I Input O Output U Pu...

Page 24: ...respectively PULL UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB FUNC DATA OUTPUT SUB FUNC ENABLE DIRECTION REGISTER SUB FUNC DIRECTION Q D r CP DEBOUNCE CLK DEBOUNCE ENABLE SUB FUNC DATA INPUT PO...

Page 25: ...D to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CLK DEBOUNCE ENABLE PORTx INPUT SUB FU...

Page 26: ...66 has just 16Kbytes program memory space Figure 11 shows a map of the lower part of the program memory After reset CPU begins execution from location 0000H Each interrupt is assigned a fixed location...

Page 27: ...hrough FFH although they are physically separate entities The lower 128bytes of RAM are present in all 8051 devices as mapped in Figure 13 The lowest 32bytes are grouped into 4 banks of 8 registers Pr...

Page 28: ...R3 R2 R1 R0 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 4...

Page 29: ...96S166 has 512bytes of XRAM and XSFR This area has no relation with RAM FLASH It can be read and written to through SFR with 8 bit unit External RAM 512 bytes Indirect Addressing 0000H 01FFH 107FH 100...

Page 30: ...CDRH T1DDRL T1DDRH P0DB P12DB 0D0H PSW P0FSRL P0FSRH P1FSRL P1FSRH P2FSRL P2FSRH 0C8H OSCCR U0CTRL1 U0CTRL2 U0CTRL3 U0STAT 0C0H EIFLAG0 T2CRL T2CRH T2ADRL T2ADRH T2BDRL T2BDRH 0B8H IP P2IO T1CRL T1CRH...

Page 31: ...T_H CRC_ADDR _START_M CRC_ADDR _START_L CRC_ADDR _END_H CRC_ADDR _END_M CRC_ADDR _END_L 1070H CRC_CON CRC_H CRC_L CRC_MNT _H CRC_MNT _L 1068H 1060H 1058H 1050H 1048H 1040H 1038H XTFLSR 1030H 1028H FEA...

Page 32: ...0 0 0 0 0 0 0 8DH Watch Dog Timer Control Register WDTCR R W 0 0 0 0 0 1 1 1 8EH Watch Dog Timer Identification Register WDTIDR W 0 0 0 0 0 0 0 0 8FH Buzzer Data Register BUZDR R W 1 1 1 1 1 1 1 1 90H...

Page 33: ...P1PU R W 0 0 0 0 0 0 0 0 AEH P2 Pull up Resistor Selection Register P2PU R W 0 0 0 0 0 0 0 0 AFH P3 Pull up Resistor Selection Register P3PU R W 0 0 0 0 0 0 0 0 B1H P1 Direction Register P1IO R W 0 0...

Page 34: ...H Program Status Word Register PSW R W 0 0 0 0 0 0 0 0 D2H P0 Function Selection Low Register P0FSRL R W 0 0 0 0 0 0 0 0 D3H P0 Function Selection High Register P0FSRH R W 0 0 0 0 0 0 0 0 D4H P1 Funct...

Page 35: ...ontrol Register 1 U1CTRL1 R W 0 0 0 0 0 0 0 0 F2H USART1 Control Register 2 U1CTRL2 R W 0 0 0 0 0 0 0 0 F3H USART1 Control Register 3 U1CTRL3 R W 0 0 0 0 0 0 0 F5H USART1 Baud Rate Generation Register...

Page 36: ...0 0 0 1 1 1022H Flash Status Register FESR R W 1 0 0 0 0 1023H Flash Time Control Register FETCR R W 0 0 0 0 0 0 0 0 1024H Flash Address Middle Register 1 FEARM1 R W 0 0 0 0 0 0 0 0 1025H Flash Addre...

Page 37: ...egister SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Register Low 82H 7 6 5 4 3 2 1 0 DPL R W R W R W R W R W R W R W R W...

Page 38: ...rpose User Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set Cleared by hardware each instruction cycle to indicate...

Page 39: ...bits are set by a system reset 5 1 3 Pull up register selection register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxPU T...

Page 40: ...on Register P1OD 92H R W 00H P1 Open drain Selection Register P1DB DFH R W 00H P1 Debounce Enable Register P1FSRH D5H R W 00H P1 Function Selection High Register P1FSRL D4H R W 00H P1 Function Selecti...

Page 41: ...r description for P0 P0 P0 Data Register 80H 7 6 5 4 3 2 1 0 P06 P05 P04 P03 P02 P01 P00 R W R W R W R W R W R W R W Initial value 00H P0 6 0 I O Data P0IO P0 Direction Register A1H 7 6 5 4 3 2 1 0 P0...

Page 42: ...4 1 0 fx 4096 1 1 LSI 128kHz P35DB Configure De bounce of P35 Port 0 Disable 1 Enable P06DB Configure De bounce of P06 Port 0 Disable 1 Enable P05DB Configure De bounce of P05 Port 0 Disable 1 Enable...

Page 43: ...nction Select 0 I O Port EINT2 function possible when input 1 AN4 Function P0FSRL Port 0 Function Selection Low Register D2H 7 6 5 4 3 2 1 0 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 R W R W R W...

Page 44: ...0 P17 P16 P15 P14 P13 P12 P11 P10 R W R W R W R W R W R W R W R W Initial value 00H P1 7 0 I O Data P1IO P1 Direction Register B1H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R W R...

Page 45: ...De bounce of P21 Port 0 Disable 1 Enable P20_DB Configure De bounce of P20 Port 0 Disable 1 Enable P13_DB Configure De bounce of P13 Port 0 Disable 1 Enable P12_DB Configure De bounce of P12 Port 0 D...

Page 46: ...iption 0 0 I O Port EC2 function possible when input 0 1 SS0 Function 1 0 AN14 Function 1 1 LED3 Function P1FSRH 5 4 P16 Function Select P1FSRH5 P1FSRH4 Description 0 0 I O Port 0 1 XCK0 Function 1 0...

Page 47: ...0 1 T2O PWM2O Function 1 0 AN10 Function 1 1 LED1 Function P1FSRL 5 4 P12 Function Select P1FSRL5 P1FSRL4 Description 0 0 I O Port EINT11 function possible when input 0 1 T1O PWM1O Function 1 0 AN9 Fu...

Page 48: ...2IO P2 Direction Register B9H 7 6 5 4 3 2 1 0 P26IO P25IO P24IO P23IO P22IO P21IO P20IO R W R W R W R W R W R W R W Initial value 00H P2IO 6 0 P2 Data I O Direction 0 Input 1 Output NOTE EC0 P26 funct...

Page 49: ...ED6 Function P2FSRL 2 1 P21 Function Select P2FSRL2 P2FSRL1 Description 0 0 I O Port EINT8 function possible when input 0 1 SS1 Function 1 0 Reserved 1 1 LED5 Function P2FSRL4 P20 Function Select 0 I...

Page 50: ...P3 7 0 I O Data P3IO P3 Direction Register 99H 7 6 5 4 3 2 1 0 P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO R W R W R W R W R W R W R W R W Initial value 00H P3IO 7 0 P3 Data I O Direction 0 Input...

Page 51: ...t 3 Function Selection Low Register 9AH 7 6 5 4 3 2 1 0 P3FSRL6 P3FSRL5 P3FSRL4 P3FSRL3 P3FSRL2 P3FSRL1 P3FSRL0 R W R W R W R W R W R W R W Initial value 00H P3FSRL6 P34 Function select 0 I O Port 1 S...

Page 52: ...four pairs of interrupt enable registers IE IE1 IE2 and IE3 Each bit of IE IE1 IE2 IE3 register individually enables disables the corresponding interrupt source Overall control is provided by bit 7 of...

Page 53: ...nterrupt 12 Interrupt 18 Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20 Interrupt 3 Interrupt 9 Interrupt 15 Interrupt 21 Interrupt 4 Interrupt 10...

Page 54: ...disable bits The external interrupt flag register EIFLAG provides the status of external interrupts EINT0 Pin EINT2 Pin EINT4 Pin FLAG0 EINT1 Pin FLAG1 FLAG2 EINT3 Pin FLAG3 FLAG4 EINT5 Pin EIPOL0H 2...

Page 55: ...Timer 2 IP1 IP IE FLAG10 FLAG11 IE2 T0OVIFR T0IFR T1IFR T2IFR EIPOL1 I2C Usart1 Rx Usart1 Tx IE1 I2CIFR ADC WT WDT BIT ADCIFR WTIFR WDTIFR BITIFR Level 0 Level 1 Level 2 Level 3 EIPOL0H L CRC CRC_FL...

Page 56: ...0033H External Interrupt 6 INT7 IE1 1 8 Maskable 003BH I2C Interrupt INT8 IE1 2 9 Maskable 0043H USART1 RX Interrupt INT9 IE1 3 10 Maskable 004BH USART1 TX Interrupt INT10 IE1 4 11 Maskable 0053H USAR...

Page 57: ...ceptance always generates at last cycle of the instruction So instead of fetching the current instruction CPU executes internally LCALL instruction and saves the PC at stack For the interrupt service...

Page 58: ...lag 0 1 Program Counter low Byte SP SP 1 M SP PCL 2 Program Counter high Byte SP SP 1 M SP PCH 3 Interrupt Vector Address occurrence Interrupt Vector Address 4 ISR Interrupt Service Routine move execu...

Page 59: ...ctive Timing of Interrupt Enable Register Case B in Figure 20 shows the effective time after controlling Interrupt Flag Registers Figure 20 Case B Effective Timing of Interrupt Flag Register Interrupt...

Page 60: ...priority than INT1 is occurred Then INT0 is served immediately and then the remaining part of INT1 service routine is executed If the priority level of INT0 is same or lower than INT1 INT0 will be ser...

Page 61: ...able Address and the Entry Address of ISR 6 9 Saving restore general purpose registers Figure 24 Saving Restore Process Diagram and Sample Source 0EH 2EH 0125H 0126H Basic Interval Timer Service Routi...

Page 62: ...and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command If an interrupt source is detected the lower 8 bit of interrupt vector INT_VEC is decided M8051W core mak...

Page 63: ...cleared to 00H If interrupts have the same priority level lower number interrupt is served first 6 11 3 External Interrupt Flag Register EIFLAG0 and EIFLAG1 External Interrupt Flag 0 Register EIFLAG0...

Page 64: ...IE3 ABH R W 00H Interrupt Enable Register 3 IP B8H R W 00H Interrupt Priority Register IP1 F8H R W 00H Interrupt Priority Register 1 EIFLAG0 C0H R W 00H External Interrupt Flag 0 Register EIPOL0L A4H...

Page 65: ...Enable or Disable External Interrupt 11 EINT11 0 Disable 1 Enable INT0E Enable or Disable External Interrupt 10 EINT10 0 Disable 1 Enable IE1 Interrupt Enable Register 1 A9H 7 6 5 4 3 2 1 0 INT11E IN...

Page 66: ...ble INT12E Enable or Disable USART0 TX Interrupt 0 Disable 1 Enable IE3 Interrupt Enable Register 3 ABH 7 6 5 4 3 2 1 0 INT23E INT22E INT21E INT20E INT19E INT18E R W R W R W R W R W R W Initial value...

Page 67: ...or automatically cleared by INT_ACK signal Writing 1 has no effect 0 External interrupt 5 6 not occurred 1 External interrupt 5 6 occurred EIFLAG0 4 0 When an External Interrupt 0 4 is occurred the f...

Page 68: ...errupt no generation 1 T0 interrupt generation EIFLAG1 6 4 When an External Interrupt 10 12 is occurred the flag becomes 1 The flag is cleared only by writing 0 to the bit or automatically cleared by...

Page 69: ...1 0 POLA POL9 POL8 POL7 R W R W R W R W R W R W R W R W Initial value 00H EIPOL2 7 0 External interrupt EINTA EINT9 EINT8 EINT7 polarity selection POLn 1 0 Description 0 0 No interrupt at any edge 0...

Page 70: ...tained from the external oscillator For this it is necessary to place external clock signal into the XIN SXIN pin and open XOUT SXOUT pin Default system clock is 16MHz INT RC Oscillator To stabilize t...

Page 71: ...1 64 1 2 1 4 1 8 M U X LIRC OSC 128kHz Stabilization Time Generation BIT clock SXIN SXOUT Sub OSC fSUB WT 2 SCLK 1 0 1 16 1 32 3 IRCS 2 0 fx 4096 fx 1024 fx 128 fx 16 M U X 3 BITCK 2 0 HIRC OSC 32MHz...

Page 72: ...Control the Operation of the Low Frequency 128kHz internal RC Oscillator at Stop mode 0 Disable operation of LSI OSC 1 Enable operation of LSI OSC IRCS 2 0 Internal RC Oscillator Post divider Selectio...

Page 73: ...s 4MHz MX_FIL_DIS Main X TAL noise canceller selection 0 Using noise filter 1 Bypass noise filter MX_ISEL 1 0 Current selective option for MX TAL MX_ISEL1 MX_ISEL0 Description 0 0 HIGH 12M 0 1 MID HIG...

Page 74: ...interrupt 8 1 BIT block diagram In this section basic interval timer of A96G166 A96A166 A96S166 is described in a block diagram 32 Prescaler 1 4096 1 16 1 1024 1 128 3 BITCK BITCNT BITIFR Overflow 8 b...

Page 75: ...s bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 BIT interrupt no generation 1 BIT interrupt generation BITCK 2 0 Select BIT clock source...

Page 76: ...me reaches 75 a watchdog interrupt can be generated The overflow time of the watchdog timer can be selected by WDTOVF 2 0 of WDTCR If the overflow occurs an internal reset is generated The WDTRC opera...

Page 77: ...elected as 50 Counting Start Window close 25 Overflow time Window open 75 Watchdog reset is occurred if 96H is written to WDTC Counter clear Start again if 96H is written to WDTC 2 WDT window open per...

Page 78: ...Time Selector WDOVF 2 0 Check Identification Window Selector WDTPDON clear WDTRTI WINDOW 1 0 INTERNAL BUS 8 8 WDT Clock TYP 4KHz stop idle DIV 32 WDT16 Bit CNT Write detector to WDTE except 96H fLSIRC...

Page 79: ...W R W R W Initial value 00H WDTC 7 0 WDT Counter Clear Others Reset occurs 10010110 WDT counter clear and start again WDTSR Watch Dog Timer Status Register 1011H 7 6 5 4 3 2 1 0 WSTATE WDTIFR R R W In...

Page 80: ...isable WDT overflow reset used 1 Watch Dog Timer RESET ON WDTPDON Operation on Stop Idle Mode 0 WDTRC operation stop in Stop Idle Mode 1 WDTRC operation in Stop Idle Mode WINDOW 1 0 Select WDT window...

Page 81: ...ounter circuits may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to increase resolution By configuring the WTDR it is possible to control...

Page 82: ...ription WTCNT Watch Timer Counter Register Read Case 89H 7 6 5 4 3 2 1 0 WTCNT6 WTCNT5 WTCNT4 WTCNT3 WTCNT2 WTCNT1 WTCNT0 R R R R R R R Initial value 00H WTCNT 6 0 WT Counter WTDR Watch Timer Data Reg...

Page 83: ...e 0 to this bit or automatically clear by INT_ACK signal Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0...

Page 84: ...T0DR T0O port toggles In addition timer 0 outputs PWM waveform through PWM0O port in the PWM mode Table 15 Timer 0 Operating Mode T0EN T0MS 1 0 T0CK 2 0 Timer 0 1 00 XXX 8 bit Timer Counter Mode 1 01...

Page 85: ...T0EN 8 bit Timer 0 Counter T0DR 8Bit Comparator T0IFR T0O PWM0O 8 bit Timer 0 Data Register INT_ACK Clear Match signal Clear Match MUX T0MS 1 0 2 To interrupt block T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0...

Page 86: ...nerated and the interrupt of timer 0 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH Then the counter continues incrementing from 00H The...

Page 87: ...NT T0PWM 00H 01H 02H 4AH FFH FEH 00H T0 Match Interrupt T0 Overflow Interrupt T0DR 1 T0DR 4AH Timer 0 clock Set T0EN T0PWM T0 Match Interrupt 2 T0DR 00H T0PWM T0 Match Interrupt 3 T0DR FFH PWM Mode T0...

Page 88: ...mer 0 output T0O waveform is not available According to EIPOL1 registers setting the external interrupt EINT10 function is chosen Of course the EINT10 pin must be set to an input port T0CDR and T0DR a...

Page 89: ...A96G166 A96A166 A96S166 User s manual 11 Timer 0 1 2 89 Figure 36 Input Capture Mode Operation for Timer 0 Figure 37 Express Timer Overflow in Capture Mode...

Page 90: ...r 0 Data Register INT_ACK Clear Clear Match MUX T0CDR 8Bit Clear EINT10 EIPOL1 1 0 FLAG10 EIFLAG1 4 INT_ACK Clear To interrupt block 2 T0MS 1 0 2 T0MS 1 0 2 Match signal T0CC Figure 38 8 bit Timer 0 B...

Page 91: ...apture Data T0CR Timer 0 Control Register B2H 7 6 5 4 3 2 1 0 T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC R W R W R W R W R W R W R W Initial value 00H T0EN Control Timer 0 0 Timer 0 disable 1 Timer 0 ena...

Page 92: ...e The clock sources are introduced below and one is selected by clock selection logic which is controlled by clock selection bits T1CK 2 0 TIMER 1 clock source fX 1 fX 2 fX 4 fX 8 fX 64 fX 2048 HSI an...

Page 93: ...automatically cleared by the match signal It can be cleared by software T1CC too The external clock EC1 counts up the timer at the rising edge If the EC1 is selected as a clock source by T1CK 2 0 EC1...

Page 94: ...11 Timer 0 1 2 A96G166 A96A166 A96S166 User s manual 94 Figure 40 16 bit Timer Counter Mode Operation Example...

Page 95: ...ing to EIPOL1 registers setting the external interrupt EINT11 function is selected EINT11 pin must be set as an input port A Match T1CC T1EN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 2048 fx 8 fx...

Page 96: ...6 Figure 42 16 bit Capture Mode Operation Example Figure 43 Express Timer Overflow 16 bit Capture Mode T1CNTH L Value Interrupt Request FLAG11 TIME 1 2 3 4 5 6 n 2 n 1 n Interrupt Interval Period 0 Co...

Page 97: ...x 2 fx 4 fx 64 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear B Match Edge Detector T1ECE EC1 Buffer Register B Comparator 16 bit A Data Register...

Page 98: ...2 M A Match 1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 1 clock Counter T1ADRH L T1 Interrupt PWM1O B Match One shot Mode...

Page 99: ...x 2 fx 4 fx 64 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear B Match Edge Detector T1ECE EC1 Buffer Register B Comparator 16 bit A Data Register...

Page 100: ...DDRH L 5 PWM1OB T1CDR T1 Clock T1DDR T1 Clock T1BPOL 0b PWM1OB T1CDR T1 Clock T1DDR T1 Clock T1BPOL 1b X X 0 1 2 4 6 7 0 TZ_Counter X 3 5 1st PERIOD 2nd PERIOD T1CDR T1 Clock T1CDR T1 Clock PWM1O 1 T1...

Page 101: ...EC1 Buffer Register B Comparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T1O PWM1O R T1EN 3 T1CK 2 0 2 T1PE A Match...

Page 102: ...ta Low Register T1DDRH DCH R W FFH Timer 1 D Data High Register 11 2 7 Register description T1ADRH Timer 1 A data High Register BDH 7 6 5 4 3 2 1 0 T1ADRH7 T1ADRH6 T1ADRH5 T1ADRH4 T1ADRH3 T1ADRH2 T1AD...

Page 103: ...CDRH 7 0 T1 C Data High Byte T1CDRL Timer 1 C Data Low Register D9H 7 6 5 4 3 2 1 0 T1CDRL7 T1CDRL6 T1CDRL5 T1CDRL4 T1CDRL3 T1CDRL2 T1CDRL1 T1CDRL0 R W R W R W R W R W R W R W R W Initial value FFH T1...

Page 104: ...2 1 0 T1CK2 T1CK1 T1CK0 T1IFR T1BPOL T1POL T1ECE T1CNTR R W R W R W R W R W R W R W R W Initial value 00H T1CK 2 0 Select Timer 1 clock source fx is main system clock frequency T1CK2 T1CK1 T1CK0 Desc...

Page 105: ...er output external clock EC2 and T1 A Match timer 1 A match signal The clock source is selected by a clock selection logic controlled by clock selection bits T2CK 2 0 TIMER 2 clock source fX 1 fX 2 fX...

Page 106: ...imer 2 occurs The T2CNTH T2CNTL values are automatically cleared by the match signal It can be cleared by software T2CC too T2MS 1 0 T2POL A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 fx 4 fx 64...

Page 107: ...A96G166 A96A166 A96S166 User s manual 11 Timer 0 1 2 107 Figure 50 16 bit Timer Counter Mode Operation Example...

Page 108: ...ot available According to EIPOL1 registers setting the external interrupt EINT12 function is selected EINT12 pin must be set as an input port A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 fx 4 fx...

Page 109: ...A96G166 A96A166 A96S166 User s manual 11 Timer 0 1 2 109 Figure 52 16 bit Capture Mode Operation Example Figure 53 Express Timer Overflow in Capture Mode...

Page 110: ...rator 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear B Match Buffer Register B Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To interrupt block A Match B...

Page 111: ...2 M A Match 1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 2 clock Counter T2ADRH L T2 Interrupt PWM2O B Match One shot Mod...

Page 112: ...erator T2O PWM2O R EINT12 T2CNTR T2EN 3 T2CK 2 0 Clear EIPOL1 5 4 FLAG12 EIFLAG1 6 INT_ACK Clear To interrupt block 2 2 T2MS 1 0 2 T1 A Match A Match T2CC T2EN A Match T2CC T2EN M U X Edge Detector EC...

Page 113: ...T2BDRH3 T2BDRH2 T2BDRH1 T2BDRH0 R W R W R W R W R W R W R W R W Initial value FFH T2BDRH 7 0 T2 B Data High Byte T2BDRL Timer 2 B Data Low Register C6H 7 6 5 4 3 2 1 0 T2BDRL7 T2BDRL6 T2BDRL5 T2BDRL4...

Page 114: ...upt occurs this bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 T2 interrupt no generation 1 T2 interrupt generation T2ECS Timer 2 External...

Page 115: ...urce clock divided by prescaler 1 BUZDR Ratio Prescaler 2 Frequency Oscillator Hz fBUZ Table 21 Buzzer Frequency at 8MHz BUZDR 7 0 Buzzer Frequency kHz BUZCR 3 1 000 BUZCR 3 1 001 BUZCR 3 1 010 BUZCR...

Page 116: ...ZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the Buzzer frequency Its resolution is 00H FFH BUZCR Buzzer Control Register 97H 7 6 5 4 3 2 1 0...

Page 117: ...et to xxx Registers ADCDRH and ADCDRL contain the result of A D conversion When the conversion is completed the result is loaded into ADCDRH and ADCDRL A D conversion status bit AFLAG is set to 1 and...

Page 118: ...ctor ADCDRH R ADCDRL R Control Logic Comparator ADSEL 3 0 Select one input pin of the assigned pins ADCLK Input Pins M U X AN0 Reference Voltage AVSS AN1 AN2 AN14 AN15 ADCIFR AFLAG INT_ACK Clear Clear...

Page 119: ...DCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4...

Page 120: ...5 Register description ADCDRH A D Converter Data High Register 9FH 7 6 5 4 3 2 1 0 ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDL11 ADDM6 ADDL10 ADDM5 ADDL9 ADDM4 ADDL8 R R R R R R R R Initial value xxH ADDM 11...

Page 121: ...n 1 ADC Interrupt generation IREF Select internal voltage reference 0 External input signal source select 1 Test only TRIG 2 0 A D Trigger Signal Selection TRIG2 TRIG1 TRIG0 Description 0 0 0 ADST 0 0...

Page 122: ...0 No effect 1 ADC Conversion Start and auto clear REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 Reserved AFLAG A D Converter Operation State This bit is cleared to 0 when the STB...

Page 123: ...master operation Up to 400 kHz data transfer speed 7 bit address Support 2 slave addresses Both master and slave operation Bus busy detection 14 1 Block Diagram Debounce enable SDA Noise Canceller de...

Page 124: ...e master to release the bus lines so that other devices can use it A high to low transition on the SDA line while SCL is high defines a START S condition A low to high transition on the SDA line while...

Page 125: ...able LOW during the HIGH period of this clock pulse When a slave is addressed by a master Address Packet and if it is unable to receive or transmit because it s performing some real time function the...

Page 126: ...W period and its HIGH period determined by the one with the shortest clock HIGH period A master may start a transfer only if the bus is free Two or more masters may generate a START condition Arbitrat...

Page 127: ...tialize I2C block condition depended on clock system I2C devices condition after system power on An application S W prepares I2C bus communication resource on RAM buffers If it is to set the start fla...

Page 128: ...ing the IICEN bit of the I2CMR register I2CMR IICEN I2C block enable 2 Reset the I2C block by setting the RESET bit of the I2CMR register I2CMR RESET Reset I2C block by S W 3 Depending on I2C devices...

Page 129: ...STOP condition or Re start condition and so on The I2C Interrupt occurs when the following cases are finished 1 As an I2C master device Sending a byte on I2CDR register after setting Start bit GCALL...

Page 130: ...ock takes master mode MASTER bit 1 and takes the read write state TMODE bit read 0 write 1 according to the data direction bit R W of device address Example software for the master mode is introduced...

Page 131: ...e If Master mode and TMODE If ACK and GCALL I2CMR ACKEN After receive data generate ACK I2CSR 0xFF Byte transmit start ELSE if ACK and TEND If Not End of Data If LAST Data I2CMR ACKEN After receive da...

Page 132: ...he next SCL clock from the master The I2C block decides the bus direction data receive transmission by using a data direction R W bit in Slave address from master The state of bus direction is set in...

Page 133: ...E1H R W 00H I2C Mode Control Register I2CSR E2H R 00H I2C Status Register I2CSCLLR E3H R W 3FH SCL Low Period Register I2CSCLHR E4H R W 3FH SCL High Period Register I2CSDAHR E5H R W 01H SDA Hold Time...

Page 134: ...ion of I2C 0 Disable interrupt operates in polling mode 1 Enable interrupt ACKEN Controls ACK signal generation at ninth SCL period Note ACK signal is output SDA 0 for the following 3 cases When recei...

Page 135: ...ion is detected NOTE1 0 No STOP condition is detected 1 STOP condition is detected SSEL This bit is set when I2C is addressed by other master NOTE1 0 I2C is not selected as slave 1 I2C is addressed by...

Page 136: ...frequency of I2C master mode fI2C is calculated by the following equation fI2C 1 tSCLK 4 SCLL SCLH 4 I2CSDAHR SDA Hold Time Register E5H 7 6 5 4 3 2 1 0 SDAH7 SDAH6 SDAH5 SDAH4 SDAH3 SDAH2 SDAH1 SDAH...

Page 137: ...ows general call address or not when I2C operates in slave mode 0 Ignore general call address 1 Allow general call address I2CSAR1 I2C Slave Address Register 1 EAH 7 6 5 4 3 2 1 0 SLA7 SLA6 SLA5 SLA4...

Page 138: ...tion Framing Error Detection Digital Low Pass Filter Three Separate Interrupts on TX Complete TX Data Register Empty and RX Complete Double Speed Asynchronous Communication Mode The USART has three ma...

Page 139: ...Checker UDATA 0 Rx UDATA 1 Rx Parity Generator Stop bit Generator UDATA Tx SSn SS Control RXC TXC UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UnCTRL1 ADDRESS CBH F1H INITIAL VALUE 0000_0000B UDRIE TXCIE RXC...

Page 140: ...mode is controlled by the U2X bit in the UnCTRL2 register The MASTER bit in UnCTRL2 register controls whether the clock source is internal Master mode output port or external Slave mode input port The...

Page 141: ...frequency of main system clock SCLK 15 4 Synchronous mode operation When synchronous mode or SPI mode is used the XCKn pin will be used as either clock input slave or clock output master The dependenc...

Page 142: ...fore the stop bits A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set...

Page 143: ...the XCKn pin will be overridden and used as a transmission clock If USART operates in SPI mode SSn pin is used as SSn input pin in slave mode or can be configured as SSn output pin in master mode This...

Page 144: ...TXC bit in USTAT register When the Transmit Complete Interrupt Enable TXCIE bit in UnCTRL2 register is set and the Global Interrupt is enabled USART Transmit Complete Interrupt is generated while TXC...

Page 145: ...her there are unread data present in the receive buffer This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty If the Receiver is disabled RXE 0...

Page 146: ...includes a clock and data recovery unit The Clock Recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frame on the RXDn pin The Data...

Page 147: ...considered to a logic 1 Data recovery process is then repeated until a complete frame is received including the first stop bit The decided bit value is stored in the receive shift register in order N...

Page 148: ...d as MOSIn for compatibility to other SPI devices 15 9 1 SPI clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers the USART has a clock...

Page 149: ...n inputs respectively At the second XCKn edge the USARTn shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave respectively Unlike the case of UCPHA 1 when UCPHA...

Page 150: ...t to the MOSIn and MISOn output of the master and slave respectively When UCPHA 1 the slave s SSn input is not required to go to its inactive high level between transfers Because the SPI logic reuses...

Page 151: ...x UBAUD 1 Calculated UBAUD 1000000 Target Baud rate 1 7 68 Error rate 0 68 UBAUD 8 Real baud rate at sysclk 16Mhz 111 111 bps 1 bit time 9us Maximum count time 9us 65536 16bit count 589 8ms USART RX S...

Page 152: ...r UnCTRL3 CDH F3H R W 00H USART Control 3 Register UnCTRL4 1018H 1019H R W 00H USART Control 4 Register UnSTAT CFH F7H R 80H USART Status Register UnBAUD FCH F5H R W FFH USART Baud Rate Generation Reg...

Page 153: ...ved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit UDORD This bit is in the same bit position with USIZE1 In SPI mode when set to one the MSB of the data byte is transmitted first When set to zero the LSB...

Page 154: ...use polling 1 When RXC is set request an interrupt WAKEIE Interrupt enable bit for Asynchronous Wake in STOP mode When device is in stop mode if RXD2 goes to LOW level an interrupt can be requested t...

Page 155: ...ee running while USART is enabled in synchronous master mode 1 XCK is active while any frame is on transferring SPISS Controls the functionality of SS pin in master SPI mode 0 SS pin is normal GPIO or...

Page 156: ...e out 0 Disable 1 Enable RTO_FLAG This bit is set when RTO count overflows This flag can generate an RTO interrupt Writing 0 to this bit position will clear RTO_FLAG 0 RTO count dose not overflow 1 RT...

Page 157: ...pt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE This flag is set when the RX pin is detected low while the CPU is in stop mode This flag can...

Page 158: ...ents of the Receive Buffer Write this register only when the UDRE flag is set In SPI or synchronous master mode write this register even if TX is not enabled to generate clock XCK FPCRn USART Floating...

Page 159: ...101EH 7 6 5 4 3 2 1 0 RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 R W R W R W R W R W R W R W R W Initial value 00H RTOCLn Receiver Time out Counter Low Register 101CH 101FH 7 6 5 4 3 2 1...

Page 160: ...3 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4K 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8K 7 0 0 15 0 0 8 3 5 16 2 1 15 0...

Page 161: ...eger count value For example If you want to use the 57600 baud rate fXIN 16MHz integer count value must be 16 36 value BAUD 1 16000000 16 57600 17 36 Here the accurate BAUD value is 16 36 To achieve t...

Page 162: ...RC FLAG is not cleared by hardware CRC TYPE 0 3 are not supported Validate is done by comparing the CRC_MNT register and the CRC register value CRC are not automatically initialized you need to calcul...

Page 163: ...T_H 1074H R W 00H CRC Monitor High Register CRC_MNT_L 1075H R W 00H CRC Monitor Low Register CRC_ADDR_START_H 1079H R W 00H CRC Start Address High Register CRC_ADDR_START_M 107AH R W 00H CRC Start Add...

Page 164: ...ration it is cleared automatically after the CRC monitoring is finished 0 CRC disable 1 CRC enable CRC_FAIL Status of CRC validate 0 Validate pass 1 Validate fail CRC_TYPE 2 0 Select the CRC input dat...

Page 165: ...RT 11 CRC_ADDR_ START 10 CRC_ADDR_ START 9 CRC_ADDR_ START 8 R W R W R W R W R W R W R W R W Initial value 00H CRC_ADDR_START_L CRC Start Address Low Register 107BH 7 6 5 4 3 2 1 0 CRC_ADDR_ START 7 C...

Page 166: ...4 3 2 1 0 CRC_ADDR_ END 7 CRC_ADDR_ END 6 CRC_ADDR_ END 5 CRC_ADDR_ END 4 CRC_ADDR_ END 3 CRC_ADDR_ END 2 CRC_ADDR_ END 1 CRC_ADDR_ END 0 R W R W R W R W R W R W R W R W Initial value 00H CRC_ADDR_ EN...

Page 167: ...abled ALL CPU operations are disabled RAM Retains Retains Basic Interval Timer Operates continuously Stops can be operated with WDTRC OSC Watch Dog Timer Operates continuously Stops can be operated wi...

Page 168: ...de Power control register is set to 01h to enter into IDLE mode In IDLE mode internal oscillation circuits remain active Oscillation continues and peripherals are operated normally but CPU stops It is...

Page 169: ...ock Sources to exit from STOP mode is hardware reset and interrupts The hardware reset re defines all control registers When awaking from STOP mode enough oscillation stabilization time is required to...

Page 170: ...is set to 1 the STOP mode is released by a certain interrupt of which interrupt enable flag 1 and the CPU jumps to the relevant interrupt service routine Even if the IE EA bit is cleared to 0 the STOP...

Page 171: ...l value 00H PCON 7 0 Power Control 01H IDLE mode enable 03H STOP mode enable Other Values Normal operation NOTES 1 To enter into IDLE mode PCON must be set to 01H 2 To enter into STOP mode PCON must b...

Page 172: ...to the Peripheral Registers A96G166 A96A166 A96S166 has five types of reset sources as shown in the followings External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 Low Voltage...

Page 173: ...e RESET function instead of the RESET IC or the RESET circuits Figure 86 Fast VDD Rising Time Figure 87 Internal RESET Release Timing On Power Up VDD nPOR Internal Signal Internal RESETB Oscillation B...

Page 174: ...igure 89 Boot Process Waveform VDD Internal nPOR PAD RESETB BIT for Configure LVR_RESETB BIT for Reset INT OSC 8 MHz 8 INT OSC 8 MHz RESET_SYS B Configure Read 1us X 256 X 28h about 10ms 1us X 4096 X...

Page 175: ...age must rise over than flash operating voltage for Configure option read Slew Rate 0 025V ms Configure option read point About 1 6V to 1 8V Configure Value is determined by Writing Option Rising sect...

Page 176: ...e state the internal reset becomes 1 The reset process step needs 5 oscillator clocks And the program execution starts at the vector address stored at address 0000H Figure 90 Timing Diagram after RESE...

Page 177: ...77V 1 88V 2 00V 2 13V 2 28V 2 46V 2 68V 2 81V 3 06V 3 21V 3 56V 3 73V 3 91V 4 25V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consum...

Page 178: ...68V 2 81V LVI Circuit LVILS 3 0 3 06V 3 21V 3 56V 3 73V 3 91V 4 25V 2 00V 2 13V 2 28V 1 88V 4 Figure 95 LVI Block Diagram VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset INT OSC 8...

Page 179: ...writing 0 to this bit or by Power On Reset 0 No detection 1 Detection OCDRF On chip debugger reset flag bit The bit reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection LVRF...

Page 180: ...0 0 1 0 1 77V 0 0 1 1 1 88V 0 1 0 0 2 00V 0 1 0 1 2 13V 0 1 1 0 2 28V 0 1 1 1 2 46V 1 0 0 0 2 68V 1 0 0 1 2 81V 1 0 1 0 3 06V 1 0 1 1 3 21V 1 1 0 0 3 56V 1 1 0 1 3 73V 1 1 1 0 3 91V 1 1 1 1 4 25V LVR...

Page 181: ...tage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVIVS 3 0 LVI Level Select LVIVS3 LVIVS2 LVIVS1 LVIVS0 Description 0 0 0 0 Not available 0 0 0 1 Not avai...

Page 182: ...a EEPROM are Mode Register FEMR Control Register FECR Status Register FESR Time Control Register FETCR Address Low Register x FEARLx Address Middle Register x FEARMx address High Register FEARH They a...

Page 183: ...mode 1 Enable program or program verify mode ERASE Enable erase or erase verify mode with VFY 0 Disable erase or erase verify mode 1 Enable erase or erase verify mode PBUFF Select page buffer 0 Desel...

Page 184: ...ion default nPBRST Reset page buffer with PBUFF It is set automatically after 1 clock PBUFF nPBRST Description 0 0 Page buffer reset 1 0 Page buffer select register reset X 1 No operation default NOTE...

Page 185: ...gh Register 1028H 7 6 5 4 3 2 1 0 ARH7 ARH6 ARH5 ARH4 ARH3 ARH2 ARH1 ARH0 W W W W W W W W Initial value 00H ARH 7 0 Flash address high NOTES 1 FEAR registers are used for program erase and auto verify...

Page 186: ...SR 7 L Read 24 bit Checksum H M L Read OCD_XDATA FEARH Read OCD_XDATA FEARM Read OCD_XDATA FEARL Set checksum read mode Write OCD_CODE 0xFAAA 0x55 Write OCD_CODE 0xF555 0xA5 Write OCD_XDATA FEMR 0x81...

Page 187: ...DATA FEARL Set checksum read mode Write OCD_CODE 0xFAAA 0x55 Write OCD_CODE 0xF555 0xA5 Write OCD_XDATA FEMR 0x81 Write OCD_CODE FETR 0x00 Write OCD_CODE FECR 0x07 Exit checksum read mode Write OCD_XD...

Page 188: ...cleared when program or erase starts Timer stops when 10 bit counter is same to FETCR PEVBSY is cleared when program erase or verify starts and set when program erase or verify stops Max program erase...

Page 189: ...e and written by byte or page One page is 32 bytes Figure 98 Flash Memory Map Figure 99 Address Configuration of Flash Memory F E A R Flash 0000h FFFFh P R O G R A M C O U N T E R MUX pgm ers vfy 16 K...

Page 190: ...ion 7 6 5 4 3 2 1 0 FEMR 4 1 FEMR 5 1 FEMR 2 FECR 6 FECR 7 ERASE VFY PGM VFY OTPE AEE AEF Figure 100 The Sequence of Page Program and Erase of Flash Memory Page Buffer Reset Page Buffer Load 0X00H Era...

Page 191: ...Request debug mode 4 Read data from Flash Enable program mode 1 Enter OCD ISP mode NOTE1 2 Set ENBDM bit of BCR 3 Enable debug and Request debug mode 4 Enter program erase mode sequence NOTE2 A Write...

Page 192: ...automatically increases by twin 5 Set write mode FEMR 1010_0001 6 Set page address FEARH FEARM FEARL 20 hx_xxxx 7 Set FETCR 8 Start program FECR 0000_1011 9 Insert one NOP operation 10 Read FESR unti...

Page 193: ...a set FEMR to 1000_1101 6 Set FETCR 7 Start bulk erase FECR 1000_1011 8 Insert one NOP operation 9 Read FESR until PEVBSY is 1 Flash OTP area read mode 1 Enter OCD ISP mode 2 Set ENBDM bit of BCR 3 En...

Page 194: ...ortant 5 Set erase mode and select OTP area FEMR 1001_0101 6 Set page address FEARH FEARM FEARL 20 hx_xxxx 7 Set FETCR 8 Start erase FECR 0000_1011 9 Insert one NOP operation 10 Read FESR until PEVBSY...

Page 195: ...sh page erase Erase cell by page Flash bulk erase Erase the whole cells Flash program verify Read cell in verify mode after programming Flash erase verify Read cell in verify mode after erase Flash pa...

Page 196: ...n only be erased to 0 with the bulk erase command and a value of more than 0x40 at FETCR Table 41 Security Policy using Lock Bits LOCK MODE USER MODE ISP MODE FLASH OTP FLASH OTP R_P R W PE BE R W PE...

Page 197: ...r area 00H FFH Protection 0 Disable Protection 1 Enable Protection RSTS Select RESETB pin 0 Disable RESETB pin P32 1 Enable RESETB pin NOTE Code write protection and Vector area protection are disable...

Page 198: ...Address 0100H 03FFH 0 0 1 1 7Kbytes Address 0100H 07FFH 0 1 0 2 7Kbytes Address 0100H 0BFFH 0 1 1 3 7Kbytes Address 0100H 0FFFH 1 0 0 13 7Kbytes Address 0100H 37FFH 1 0 1 14 7Kbytes Address 0100H 3BF...

Page 199: ...ea OTP area R W PE BE R W PE BE LOCKPWS 0 O O O O O O O O LOCKPWS 1 X X X X note X X X NOTES Page 3 PASSWORD OTP Data read as 0x00 The other page is readable ordinarily 1 R Read 2 W Write 3 PE Page er...

Page 200: ...e below 1 Press config button 2 Check Password box and Change the Password 0 11byte 3 Reset the device please enter the password If the password is correct the device is accessible Otherwise the devic...

Page 201: ...Power Dissipation PT 600 mW Storage temperature TSTG 65 150 C NOTE Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and...

Page 202: ...get worse 2 Zero offset error is the difference between 000000000000 and the converted output for zero input voltage VSS 3 Full scale error is the difference between 111111111111 and the converted out...

Page 203: ...1 8V 5 5V VSS 0V Parameter Symbol Conditions MIN TYP MAX Unit VDC1 55 reference voltage VDC1 55 1 55 V 20 5 Power on reset characteristics Table 48 Power on Reset Characteristics TA 40 C 85 C or TA 40...

Page 204: ...cept 1 61 1 68 1 77V because the minimum operating voltage is 1 8V VLVR VLVI can be measured when voltage drops falling level 1 61 1 75 V 1 55 1 68 1 81 1 63 1 77 1 91 1 73 1 88 2 03 1 84 2 00 2 16 1...

Page 205: ...10 C to 70 C 2 0 TA 40 C to 85 C 2 5 TA 40 C to 105 C 5 0 Clock duty ratio TOD 40 50 60 Stabilization time THFS 100 us IRC current IIRC Enable 0 2 mA Disable 0 1 uA NOTE A 0 1uF bypass capacitor shoul...

Page 206: ...put low leakage current IIL All input ports VDD 5 0V 1 uA Pull Up resistor RPU1 VI 0V TA 25 C All Input ports VDD 5 0V 25 50 100 K OSC feedback resistor RX1 XIN VSS XOUT Floating TA 25 C VDD 5V 0 76 1...

Page 207: ...Table 53 AC Characteristics TA 40 C 85 C or TA 40 C 105 C VDD 1 8V 5 5V Parameter Symbol Conditions MIN TYP MAX Unit RESETB input low width tRSL Input VDD 5V 10 us Interrupt input high low width tINT...

Page 208: ...s Clock XCK low time tXCKL 2 x tSCLK 514 x tSCLK ns Lead time Master Slave tLEAD tLEAD 0 5 x tXCK 2 x tSCLK 0 5 x tXCK ns Lag time Master Slave tLAG tLAG 0 5 x tXCK 2 x tSCLK 0 5 x tXCK ns Data setup...

Page 209: ...igure 106 SPI Synchronous master mode timing UCPHA 1 MSB first XCK0 UCPOL 1 OUTPUT MOSI OUTPUT MISO INPUT tXCK 0 8VDD 0 2VDD tSOM XCK0 UCPOL 0 OUTPUT tXCKH tXCKL SS0 OUTPUT MSB LSB LSB MSB tSIM tHIM t...

Page 210: ...LSB Figure 108 SPI Synchronous slave mode timing UCPHA 1 MSB first XCK0 UCPOL 1 OUTPUT MOSI OUTPUT MISO INPUT tXCK 0 8VDD 0 2VDD tHOM XCK0 UCPOL 0 OUTPUT tXCKH tXCKL SS0 OUTPUT MSB LSB LSB MSB tSIM t...

Page 211: ...00 ns Output clock high Low pulse width tSCKH tSCKL Internal SCK source 70 ns Input clock high Low pulse width External SCK source 70 ns First output clock delay time tFOD Internal External SCK source...

Page 212: ...Clock high pulse width tSCLH 4 0 0 6 us Clock low pulse width tSCLL 4 7 1 3 Bus free time tBF 4 7 1 3 Start condition setup time tSTSU 4 7 0 6 Start condition hold time tSTHD 4 0 0 6 Stop condition s...

Page 213: ...uA Idle Mode Watchdog Timer Active VDD INT Request Execution of STOP Instruction Data Retention Stop Mode Normal Operating Mode 0 8VDD tWAIT VDDDR NOTE tWAIT is the same as the selected bit overflow o...

Page 214: ...te protection time tFHL 2 5 2 7 Page buffer reset time tFBR 5 us Flash programming frequency fPGM 0 4 MHz Endurance of Write Erase NFWE 30 000 times NOTE During a flash operation SCLK 1 0 of SCCR must...

Page 215: ...V 5 5V Oscillator Parameter Condition MIN TYP MAX Unit Crystal Main oscillation frequency 2 2V 5 5V 4 10 0 MHz 2 4V 5 5V 4 12 0 Ceramic Oscillator Main oscillation frequency 2 0V 5 5V 4 10 0 MHz 2 4V...

Page 216: ...llator Characteristics TA 40 C 85 C or TA 40 C 105 C VDD 1 8V 5 5V Oscillator Parameter Condition MIN TYP MAX Unit Crystal Sub oscillation frequency 1 8V 5 5V 32 32 768 38 kHz External Clock SXIN inpu...

Page 217: ...0 Ceramic 10 ms External clock fXIN 4 to 12MHz XIN input high and low width tXH tXL 42 1250 ns tXH tXL XIN 0 2VDD 0 8VDD 1 fXIN Figure 117 Clock Timing Measurement at XIN 20 20 Sub oscillation charact...

Page 218: ...capacitor should be within 1cm from the VDD pin of MCU on the PCB layout This 0 01uF capacitor is alternatively for noise immunity X tal SXOUT SXIN 32 768kHz The main and sub crystal should be within...

Page 219: ...operating range e g out of specified VDD range This is only for providing information and devices are guaranteed to operate properly only within the specified range The data presented in this section...

Page 220: ...20 Electrical characteristics A96G166 A96A166 A96S166 User s manual 220 Figure 122 IDLE IDD2 Current Figure 123 SUB RUN IDD3 Current...

Page 221: ...A96G166 A96A166 A96S166 User s manual 20 Electrical characteristics 221 Figure 124 SUB IDLE IDD4 Current Figure 125 SUB IDLE IDD4 Current...

Page 222: ...information A96G166 A96A166 A96S166 User s manual 222 21 Package information This chapter provides A96G166 A96A166 A96S166 package information 21 1 16 SOPN package information Figure 126 16 SOPN Packa...

Page 223: ...A96G166 A96A166 A96S166 User s manual 21 Package information 223 21 2 20 TSSOP package information Figure 127 20 TSSOP Package Outline...

Page 224: ...21 Package information A96G166 A96A166 A96S166 User s manual 224 21 3 20 SOP package information Figure 128 20 SOP Package Outline...

Page 225: ...A96G166 A96A166 A96S166 User s manual 21 Package information 225 21 4 24 QFN package information Figure 129 24 QFN Package Outline...

Page 226: ...21 Package information A96G166 A96A166 A96S166 User s manual 226 21 5 28 SOP package information Figure 130 28 SOP Package Outline...

Page 227: ...A96G166 A96A166 A96S166 User s manual 21 Package information 227 21 6 32 LQFP package information Figure 131 32 LQFP Package Outline...

Page 228: ...er The OCD emulator supports ABOV s 8051 series MCU emulation The OCD uses two wires interfacing between PC and MCU which is attached to user s system The OCD can read or change the value of MCU s int...

Page 229: ...22 3 2 OCD emulator OCD emulator allows a user to write code on the device too since OCD debugger supports ISP In System Programming It doesn t require additional H W except developer s target system...

Page 230: ...nd corresponding I O status Table 64 Pins for Flash Programming Pin name Main chip pin name During programming I O Description DSCL P01 I Serial clock pin Input only pin DSDA P00 I O Serial data pin O...

Page 231: ...tant for proper programming To application circuit DSCL I DSDA I O R1 2k 5k To application circuit R2 2k 5k VDD VSS E PGM E GANG4 E GANG6 NOTES 1 In on board programming mode very high speed signal wi...

Page 232: ...Features Two wire external interface 1 for serial clock input 1 for bi directional serial data bus Debugger accesses All internal peripherals Internal data RAM Program Counter Flash memory and data E...

Page 233: ...cknowledge bit as 0 when transmission for 8 bit data and its parity has no error When transmitter has no acknowledge Acknowledge bit is 1 at tenth clock error process is executed in transmitter When a...

Page 234: ...22 Development tools A96G166 A96A166 A96S166 User s manual 234 Packet transmission timing Figure 138 Data Transfer on Twin Bus Figure 139 Bit Transfer on Serial Bus Figure 140 Start and Stop Condition...

Page 235: ...A96G166 A96A166 A96S166 User s manual 22 Development tools 235 Figure 141 Acknowledge on Serial Bus Figure 142 Clock Synchronization during Wait Procedure...

Page 236: ...22 Development tools A96G166 A96A166 A96S166 User s manual 236 Connection of transmission Two pin interface connection uses open drain wire AND bidirectional I O Figure 143 Connection of Transmission...

Page 237: ...66FD 3 1 1 8 inputs 18 4 20 SOP A96A166FD 3 2 1 10 inputs 18 2 20 SOP A96G166FR 3 1 1 8 inputs 18 4 20 TSSOP A96S166FR 3 1 1 8 inputs 18 4 20 TSSOP A96G166AE 3 2 1 7 inputs 14 3 16 SOPN A96G166KN2 16K...

Page 238: ...S Special Pin Count K 32 pin G 28 pin L 24 pin F 20 pin Package Type N LQFP 0 8mm Pin Pitch U QFN D SOP R TSSOP Temperature none 40 C 85 C 2 40 C 105 C Product Information N Internal management code P...

Page 239: ...A dir Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1...

Page 240: ...R indirect memory to A 1 1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F...

Page 241: ...7 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 A7 MOV Ri data Move immediate to indirect memory...

Page 242: ...1 C2 SETB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPL C Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit invers...

Page 243: ...rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Ju...

Page 244: ...emory 1 2 A5 TRAP Software break command 1 1 A5 In the above table entries such as E8 EF indicate continuous blocks of hex opcodes used for 8 different registers Register numbers of which are defined...

Page 245: ...ted AVREF at Figure 58 12 bit ADC Block Diagram Deleted Figure 58 A D Power AVREF Pin with a Capacitor Changed the maximum analog input voltage to VDD at Table 45 A D Converter Characteristics Updated...

Page 246: ...87 Internal RESET Release Timing On Power Up 2021 01 13 1 10 Added a new device of A96A166FD Modified the bit position of EIPOL1 at 6 11 6 Interrupt register description Modified the invalid number of...

Page 247: ...and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications ABOV and the ABOV logo are trademarks of ABOV All other product or...

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