Abov A96G166, User Manual, Page: 113 / 247

A96G166/A96A166/A96S166 User’s manual 11. Timer 0/1/2
113
11.3.6 Register description
T2ADRH (Timer 2 A data High Register): C5H
7 6 5 4 3 2 1 0
T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value: FFH
T2ADRH[7:0] T2 A Data High Byte
T2ADRL (Timer 2 A Data Low Register): C4H
7 6 5 4 3 2 1 0
T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value: FFH
T2ADRL[7:0] T2 A Data Low Byte
NOTE: Do not write
“0000H” in the T2ADRH/T2ADRL register
when PPG mode.
T2BDRH (Timer 2 B Data High Register): C7H
7 6 5 4 3 2 1 0
T2BDRH7 T2BDRH6 T2BDRH5 T2BDRH4 T2BDRH3 T2BDRH2 T2BDRH1 T2BDRH0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value: FFH
T2BDRH[7:0] T2 B Data High Byte
T2BDRL (Timer 2 B Data Low Register): C6H
7 6 5 4 3 2 1 0
T2BDRL7 T2BDRL6 T2BDRL5 T2BDRL4 T2BDRL3 T2BDRL2 T2BDRL1 T2BDRL0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value: FFH
T2BDRL[7:0] T2 B Data Low
T2CRH (Timer 2ControlHigh Register): C3H
7 6 5 4 3 2 1 0
T2EN
–
T2MS1 T2MS0
– – –
T2CC
R/W
–
R/W R/W
– – –
R/W
Initial value: 00H
T2EN Control Timer 2
0
Timer 2 disable
1 Timer 2 enable (Counter clear and start)
T2MS[1:0] Control Timer 2 Operation Mode
T2MS1
T2MS0 Description
0 0 Timer/counter mode (T2O: toggle at A match)
0 1 Capture mode (The A match interrupt can
occur)
1 0 PPG one-shot mode (PWM2O)
1 1 PPG repeat mode (PWM2O)
T2CC Clear Timer 2 Counter
0
No effect
1 Clear the Timer 2 counter (When write, automatically
cleared “0” after being cleared counter)