A96G166/A96A166/A96S166 User’s manual
15. USART 0/1
143
15.6
Parity bit
Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of
the exclusive-or is inverted. The parity bit is located between St + bits and first stop bit of a serial
frame.
P
even
= D
n-1
^ … ^ D
3
^ D
2
^ D
1
^ D
0
^ 0
P
odd
= D
n-1
^ … ^ D
3
^ D
2
^ D
1
^ D
0
^ 1
P
even
: Parity bit using even parity
P
odd
: Parity bit using odd parity
D
n
: Data bit n of the character
15.7
USART transmitter
USART transmitter is enabled by setting the TXE bit in UnCTRL1 register. When the Transmitter is
enabled, normal port operation of TXDn pin is overridden by serial output pin of the USART. Baud
rate, operation mode and frame format must be setup once before doing any transmissions.
If synchronous or SPI operation is used, a clock on the XCKn pin will be overridden and used as a
transmission clock. If USART operates in SPI mode, SSn pin is used as SSn input pin in slave mode
or can be configured as SSn output pin in master mode. This can be done by setting SPISS bit in
UCTRL3 register.
15.7.1
Sending Tx data
Data transmission is initiated by loading the transmit buffer (UDATA register I/O location) with the
data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift
register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state
or immediately after the last stop bit of the previous frame is transmitted.
When the shift register is loaded with new data, it will transfer one complete frame at the settings of
control registers. If the 9-bit characters are used in asynchronous or synchronous operation mode
(USIZE[2:0] = 7), the ninth bit must be written to the TX8 bit in UnCTRL3 register before loading
transmit buffer (UDATA register).