
A96G166/A96A166/A96S166 User’s manual
11. Timer 0/1/2
103
T1BDRL (Timer 1 B Data Low Register): BEH
7
6
5
4
3
2
1
0
T1BDRL7
T1BDRL6
T1BDRL5
T1BDRL4
T1BDRL3
T1BDRL2
T1BDRL1
T1BDRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1BDRL[7:0]
T1 B Data Low Byte
T1CDRH (Timer 1 C data High Register): DAH
7
6
5
4
3
2
1
0
T1CDRH7
T1CDRH6
T1CDRH5
T1CDRH4
T1CDRH3
T1CDRH2
T1CDRH1
T1CDRH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1CDRH[7:0]
T1 C Data High Byte
T1CDRL (Timer 1 C Data Low Register): D9H
7
6
5
4
3
2
1
0
T1CDRL7
T1CDRL6
T1CDRL5
T1CDRL4
T1CDRL3
T1CDRL2
T1CDRL1
T1CDRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1CDRL[7:0]
T1 C Data Low Byte
T1DDRH (Timer 1 D data High Register): DCH
7
6
5
4
3
2
1
0
T1DDRH7
T1DDRH6
T1DDRH5
T1DDRH4
T1DDRH3
T1DDRH2
T1DDRH1
T1DDRH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1DDRH[7:0]
T1 D Data High Byte
T1DDRL (Timer 1 D Data Low Register): DBH
7
6
5
4
3
2
1
0
T1DDRL7
T1DDRL6
T1DDRL5
T1DDRL4
T1DDRL3
T1DDRL2
T1DDRL1
T1DDRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1DDRL[7:0]
T1 D Data Low Byte