14. I2C
A96G166/A96A166/A96S166 User’s manual
128
NOTE:
When an I2C interrupt is generated by I2C block, IIF flag in I2CMR register is set and it is cleared by
writing any value to I2CSR. When I2C interrupt occurs, the SCL line is hold LOW for reading/writing
I2CDR register and control I2CMR until writing any value to I2CSR. When the IIF flag is set, the I2CSR
contains a value for the state of the I2C bus. According to the value in I2CSR, software can decide what
to do next.
I2C can operate in four modes by configuring master/slave, transmitter/receiver.
14.7.1
I2C block initialization process
After power ON, it is necessary to initialize the I2C block because the I2C block provides I2C Slave
device service.
1.
The I2C block starts operation (operation clock active) by setting the IICEN bit of the I2CMR
register.
I2CMR = IICEN;
// I2C block enable
2.
Reset the I2C block by setting the RESET bit of the I2CMR register.
I2CMR = RESET;
// Reset I2C block by S/W
3.
Depending on I2C devices, I2C SCL max clock will be defined and the value of SCL low
/high time and SDA hold time will be written on the I2CSCLLR, the I2CSCLHR, and the
I2CSDAHR as shown in Figure 69.
SDA
SCL
I2CSCLLR
t
scll
I2CSCLHR
(t
sclh
)
I2CSDAHR
(t
sdah
)
Figure 69. I2C SCL Max Clock, SCL, SDA Settings
The timing values are calculated as the follow formula
tscll
= tsysclk (4xI21)
→
SCL clock low time
tsclh
= tsysclk (4xI23)
→
SCL clock High time
tsdah
= tsysclk (I24)
→
SDA data hold time after falling edge of SCL
* tsysclk = system clock timing
For example, if the I2C clock of 100kHz and the system clock of 4MHz are used, each of tscll
and tsclhtimes is 5us, and tsdah is 2.5 us.
I2CSCLLR = 5; I2CSCLHR = 4; I2CSDAHR = 6;
4.
Decide I2C Slave device address and write the address to I2CSAR
I2CSAR = SELF_ADDRESS;