abaco systems FM680, User Manual

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FM680 User Manual r1.7
FM680 www.abaco.com Page 7 of 32
Virtex-5
(FPGA A)
2
2
54
8
8
GPIO
Only on LX550T
and SX475T
Virtex-6
(FPGA B)
GPIO
GPIO
GPIO
CC
CC
GPIO
GPIO
GPIO
GPIO
Figure 2: Inter-FPGA Interface
By default Abaco delivers a reference design that uses the interfpga bus to allow high speed
data transfer and command distribution between the PCIexpress interface in the FPGA A
and the FPGA B.
The standard reference design does not implement the PN4 connection since those
connections will depend on the user specific application. The user is free to modify the
reference design and add specific features in FPGA A and FPGA B.
The connections between the FPGA A and FPGA B are described in the following table.
Table 2: interFPGA connections
net name
FPGA A
bank
FPGA A
IO voltage
FPGA A
ball
FPGA B
bank
FPGA B
IO voltage
FPGA B
ball
INTER_FPGA0 1 BLAST0_VIO A7 34 BLAST0_VIO AU13
INTER_FPGA1 1 BLAST0_VIO A6 34 BLAST0_VIO AR13
INTER_FPGA2 1 BLAST0_VIO E9 34 BLAST0_VIO AP13
INTER_FPGA3 1 BLAST0_VIO D8 34 BLAST0_VIO AN13
INTER_FPGA4 1 BLAST0_VIO D10 34 BLAST0_VIO AM13
INTER_FPGA5 1 BLAST0_VIO D9 33 BLAST0_VIO AK14
INTER_FPGA6 1 BLAST0_VIO C8 33 BLAST0_VIO AL14
INTER_FPGA7 1 BLAST0_VIO C7 33 BLAST0_VIO AM14
INTER_FPGA8 1 BLAST0_VIO B9 34 BLAST0_VIO AN14
INTER_FPGA9 1 BLAST0_VIO F8 34 BLAST0_VIO AR14
INTER_FPGA10 1 BLAST0_VIO B6 34 BLAST0_VIO AT14
INTER_FPGA11 1 BLAST0_VIO C6 34 BLAST0_VIO AV14
INTER_FPGA12 1 BLAST0_VIO A8 34 BLAST0_VIO BA14
INTER_FPGA13 1 BLAST0_VIO F7 34 BLAST0_VIO BB14
INTER_FPGA14 1 BLAST0_VIO A9 34 BLAST0_VIO BA15
INTER_FPGA15 1 BLAST0_VIO D7 34 BLAST0_VIO AY15
INTER_FPGA16 1 BLAST0_VIO E7 34 BLAST0_VIO AW15
INTER_FPGA17 1 BLAST0_VIO B10 34 BLAST0_VIO AV15
INTER_FPGA18 1 BLAST0_VIO C10 34 BLAST0_VIO AR15
INTER_FPGA19 11 BLAST0_VIO D13 34 BLAST0_VIO AP15
INTER_FPGA20 11 BLAST0_VIO D14 33 BLAST0_VIO AN15
INTER_FPGA21 11 BLAST0_VIO E15 33 BLAST0_VIO AL15
INTER_FPGA22 11 BLAST0_VIO D15 33 BLAST0_VIO AK15