FM680 User Manual
r1.7
FM680
Page 6 of 32
BLAST, Board Level Advanced Scalable Technology, is a small PCB module that allows
customization of the FM680 in memory extensions, processing units and communication
interfaces. For more information about the available BLASTs on the FM680 please consult
the following page: BLAST modules
4 Installation
4.1 Requirements and handling instructions
•
The FM680 must be installed on a motherboard compliant to the VITA 42.3 standard.
•
Do not flex the board
•
Observe ESD precautions when handling the board to prevent electrostatic
discharges.
•
Do not install the FM680 while the motherboard is powered up.
4.2 Firmware and software
Drivers, API libraries and a program example working in combination with a pre-programmed
firmware for both FPGAs are provided. The FM680 is delivered with an interface to the Xilinx
PCI-e endpoint core in the Virtex-5 device as well as an example VHDL design in the Virtex-
6 device so users can start performing high bandwidth data transfers over the PCI bus right
out of the box. For more information about software installation and FPGA firmware, please
refer the 4FM Get Started Guide.
5 Design
5.1 FPGA devices
The Virtex-5 and Virtex-6 FPGA devices interface to the various resources on the FM680 as
shown on Figure 1. They also interconnect to each other via 58 general purpose pins
including 4 clock pins (2 pairs, one in each direction, 100
Ω
terminated). A 16 bits single
ended bus is also available between the two FPGA devices for communication with the Pn4
bus or general purpose communication.
5.1.1 Virtex-5 device family and package
The Virtex-5 device is from the Virtex-5 LX family. It can be either an XC5VLX20T
or
XC5VLX30T
in a Fineline Ball Grid array with 323 balls (FF323).
5.1.2 Virtex-6 device family and package
The Virtex-6 device is dedicated to Digital Signal Processing, video processing or
communication applications and can be chosen from the SXT or LXT family devices. Its
package is based on Fineline Ball Grid array with 1759 balls. In terms of logic and dedicated
DSP resources, the FPGA B can be chosen from the following types: LX240T, LX550T,
SX315T and the SX475T (FF1759).
5.2 Inter-FPGA interface
The Virtex-5 device is connected to the Virtex-6 device using a 54 pin bus plus 2 differential
clock signals. Also there are 16 single ended pins available that can be used as general
purpose IO or as a connection to the Pn4 bus. Please be aware that 8 of those extra bits are
available only on the SX475T and the LX550T FPGA types.
