Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
02/26/10
1.0
Initial Xilinx release.
06/11/10
1.1
Removed references to specific release numbers for the ISE Design Suite, where
applicable. Replaced
,
, and
Removed update DVD from
. Added “in loopback mode” to
. Removed DDR3 from Raw Data Path bullet in
a on
b on
, changed the minimum value of the range from 128 to 64 for the XAUI
and Raw Data paths and changed the Raw Data path option to one Packet Size instead
of a minimum and a maximum. In
c on
, indicated to click
Start test
.
Added the note under
. Replaced the “ISE 11.1 Software Installation” and
“ISE 11.4 Software Update Installation” sections with a link to the Installation, Licensing,
and Release Notes document. In
, removed the ISE Design Suite release
number from the path. In
Modifying the Virtex-6 FPGA Targeted Reference Design
,
added the note on
. Changed the command in
c on
. Changed the
names of the BIT and MCS files in
. Removed “double-click” from the
Windows based script in
. Removed sentence about the command
shell opening from
. Added the
section.
08/10/10
1.2
In
, changed the filename to
mig3_5.xco
from
mig3_4.xco
. In
, changed the implementation software tool entry to ISE Design Suite.
10/05/10
1.3
Added information for AXI4 protocol.
07/06/11
1.4
Removed descriptions of Virtex-6 FPGA Connectivity TRD being available in non-AXI4
protocol version throughout. Replaced v6_trd_quickstart with v6_trd_lin_quickstart.
Added Windows platform to
Board and Connectivity Targeted Reference Design
. Added
. Added
Содержание Virtex-6 FPGA
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