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Virtex-6 FPGA Connectivity Kit Getting Started

UG664 (v1.4) July 6, 2011

Getting Started with the Connectivity Targeted Reference Design Demo

16. Performance Monitor Application: Verify the board status.

Click on the

System Status

tab to verify the status of the ML605 board and the

PCIe link (see

Figure 22

Link Status: Up

This confirms that the PCIe link is up and a PCIe connection is established
between the Virtex-6 FPGA Endpoint for PCI Express and the PC
motherboard chipset.

Link Speed: 5.0 Gbps

This confirms that the PCIe link is operating at line rate speeds per PCI
Express, v2.0.

Link Width: x4

This confirms that the PCIe link is trained as a x4 link.

X-Ref Target - Figure 22

Figure 22:

Verify Board Status in the Performance Monitor

UG664_0

_090

Содержание Virtex-6 FPGA

Страница 1: ...Virtex 6 FPGA Connectivity Kit Getting Started Guide UG664 v1 4 July 6 2011 XPN 0402826 03...

Страница 2: ...cluded herein are trademarks of Xilinx in the United States and other countries PCI PCIe and PCI Express are trademarks of PCI SIG and used under license All other trademarks are the property of their...

Страница 3: ...ance Monitor and Status GUI and Figure 26 Run v6_trd_quickstart Corrected coregen command in step 4c on page 42 Updated ending step instruction from step 8 to step 6 in Test Setup Added Windows Driver...

Страница 4: ...Virtex 6 FPGA Connectivity Kit Getting Started www xilinx com UG664 v1 4 July 6 2011...

Страница 5: ...3 Installation and Licensing of ISE Design Suite 36 Downloading and Installing Tool Licenses 36 Modifying the Virtex 6 FPGA Targeted Reference Design 42 Hardware Modifications 42 Test Setup 44 Softwar...

Страница 6: ...6 www xilinx com Virtex 6 FPGA Connectivity Kit Getting Started UG664 v1 4 July 6 2011...

Страница 7: ...arch the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support Use this site for technical sup...

Страница 8: ...8 www xilinx com Virtex 6 FPGA Connectivity Kit Getting Started UG664 v1 4 July 6 2011 Preface About This Guide...

Страница 9: ...ormation only For the latest information see the Xilinx ISE Design Suite Connectivity Kit Contents This section describes the kit deliverables provided in the box and indicates what can be found on th...

Страница 10: ...ard bill of materials BOM Additional detailed documentation Technical Support http www xilinx com support Getting Started with the Connectivity Targeted Reference Design Demo The Virtex 6 FPGA Connect...

Страница 11: ...LogiCORE IP that utilizes serial I O transceivers to provide a throughput of up to 10 Gb s XAUI TX and XAUI RX blocks align data as per the XGMII format Control logic to interface between the DMA and...

Страница 12: ...1 refer to Getting Started with the Virtex 6 FPGA IBERT Reference Design page 64 to alternately bring up the ML605 board included in the Virtex 6 FPGA Connectivity Kit Otherwise continue with the PCIe...

Страница 13: ...y 6 2011 Getting Started with the Connectivity Targeted Reference Design Demo X Ref Target Figure 2 Figure 2 ML605 and FMC Connectivity Daughter Card X Ref Target Figure 3 Figure 3 CX4 Connector UG664...

Страница 14: ...e ON position away from the bracket edge of the ML605 board as shown in Figure 4 6 Hardware Setup III Insert the ML605 board into an empty PCIe slot a Identify a x8 or a x16 PCIe slot on the PC mother...

Страница 15: ...rdware Wizard a Power the PC system on and wait for the operating system OS to load b The system recognizes a new PCIe endpoint card connected to it and starts the Found New Hardware Wizard c Click on...

Страница 16: ...vered with the connectivity kit b Insert the USB flash drive into a USB connector of the PC system and copy the v6_pcie_10Gdma_ddr3_xaui_axi folder to the PC system Note Ensure that the path where the...

Страница 17: ...6 2011 Getting Started with the Connectivity Targeted Reference Design Demo c The InstallShield wizard for the Virtex 6 FPGA Connectivity TRD is launched Figure 8 Click on Next to select the setup typ...

Страница 18: ...h the Connectivity Targeted Reference Design Demo d Select Typical to set C Program Files as the destination directory where driver files will reside Click on Next and confirm the Setup Type selection...

Страница 19: ...llShield wizard completes click on Finish Figure 10 At the end of this install process the driver and GUI files are copied to the C Program Files Xilinx Inc Virtex6 folder Also a shortcut to the Xilin...

Страница 20: ...July 6 2011 Getting Started with the Connectivity Targeted Reference Design Demo 10 Load the drivers a After the InstallShield wizard completes Add Hardware Wizard is launched Figure 11 Click on Next...

Страница 21: ...are wizard finds a PCI Simple Communications Controller VID 10EE DID 6042 and prompts a search of the driver through the Windows Update website Figure 12 Select No not this time and click on Next to g...

Страница 22: ...geted Reference Design Demo c Select Install the software automatically and click on Next The system associates the Xilinx DMA driver to the PCI Simple Communications Controller Click on Finish to pro...

Страница 23: ...vity Targeted Reference Design Demo d Select No not this time for the driver to be searched on the Windows Update website and click on Next to get the driver files available on the system Figure 14 No...

Страница 24: ...rted with the Connectivity Targeted Reference Design Demo e Select Install the software automatically and click on Next to install the Xilinx Raw Data driver Figure 15 Click on Finish to proceed to in...

Страница 25: ...vity Targeted Reference Design Demo f Select No not this time for the driver to be searched on the Windows Update website and click on Next to get the driver files available on the system Figure 16 No...

Страница 26: ...1 4 July 6 2011 Getting Started with the Connectivity Targeted Reference Design Demo g Select Install the software automatically and click on Next to install the Xilinx XAUI driver Figure 17 Click on...

Страница 27: ..._setup exe again causes drivers to uninstall and clean the install folders 11 Launch the GUI a Double click on the xpmon icon on the desktop to launch the Performance Monitor application Figure 19 Pro...

Страница 28: ...20 are displayed on power up Wait for the login screen to be displayed This could take two to three minutes or longer depending on system configuration b Click Login to enter The desktop should appear...

Страница 29: ...ance Monitor application a Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi folder b Double click v6_trd_lin_quickstart to build the kernel objects load the device driver and launch the Performance Monito...

Страница 30: ...oard and the PCIe link see Figure 22 Link Status Up This confirms that the PCIe link is up and a PCIe connection is established between the Virtex 6 FPGA Endpoint for PCI Express and the PC motherboar...

Страница 31: ...tion Start the data traffic a To enable the XAUI datapath click Start Test as shown in Figure 23 This enables the driver to start generating the data traffic for the DMA channel connected to the XAUI...

Страница 32: ...e Raw Data path together is approximately 9 Gbps c Verify there are no buffer descriptor errors for error free operation Congratulations The Virtex 6 FPGA Connectivity Kit is now set up The pre built...

Страница 33: ...Performance Monitor for the Virtex 6 FPGA Connectivity TRD In Windows a Double click the xpmon icon on the desktop to launch the Performance Monitor application In Linux a Navigate to the v6_pcie_10Gd...

Страница 34: ...ity TRD 3 Execute the test and view payload statistics in Performance Monitor a Click Start Test to start the performance test b View the payload statistics to review data transfers on the XAUI Path a...

Страница 35: ...26 and click Start test Then view the payload statistics to review data transfers on the XAUI Path and Raw Data Path channels of the DMA engine Note For packet sizes equal to 64 or 128 bytes the thro...

Страница 36: ...PCI Express Installation and Licensing of ISE Design Suite This Virtex 6 FPGA Connectivity Kit comes with an entitlement to a full seat of the ISE Design Suite Embedded Edition that is device locked t...

Страница 37: ...r service for access to the account at http www xilinx com support techsup tappinfo htm 3 After logging in verify the shipping address if prompted Click Next after the shipping address has been verifi...

Страница 38: ...want to select their Disk ID or Wireless Ethernet card Host ID Laptops on docking stations might have three Ethernet Host IDs from which to choose If a docking station Host ID is selected then the lic...

Страница 39: ...ite 6 Review the license request as shown in Figure 31 and click Next 7 The generated license is e mailed to the user in an e mail similar to the one shown in Figure 32 X Ref Target Figure 31 Figure 3...

Страница 40: ...License Manager Start Programs ISE Design Suite Manage Xilinx Licenses and click Copy License to install the license on the computer 9 Navigate to the Xilinx lic file location and select it see Figure...

Страница 41: ...G631 ISE Design Suite Installation Licensing and Release Notes located on the Xilinx documentation site at http www xilinx com support documentation Now that the FPGA based connectivity demonstration...

Страница 42: ...ed 2 Copy the contents of the included USB stick into a local directory on this machine 3 Make design changes a Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi design source directory b Edit the v6_pcie_...

Страница 43: ...ogram the FPGA using Platform Flash refer to the jumper settings detailed in step 4 of Hardware Demonstration Setup Instructions page 12 c For all other ML605 switch and jumper settings keep them at t...

Страница 44: ...nes d After successful completion the Programmed successfully message should appear e Turn off the power switch and remove the power connector f Carefully remove the mini USB cable The Virtex 6 FPGA C...

Страница 45: ...g xdma_Inst Add the following entry for Windows XP xdma DRVDESC xdma_Inst PCI VEN_19aa DEV_6042 d With this change the driver also supports a device with Vendor ID 19AA and Device ID 6042 Save the cha...

Страница 46: ...the driver file xdma sys is available under objfre_wxp_x86 objchk_wxp_x86 i386 depending on the build environment selected The Setup Information file xdma inf is also available in the same directory...

Страница 47: ...nf is also available in the same directory e Compile Raw Data path code Navigate to the windows_driver xraw directory and execute the following build w ceZ This command invokes the Microsoft make rout...

Страница 48: ...ith xaui sys type System File and xaui inf type Setup Information from the XAUI driver compiled area c Make a folder called xraw and populate it with xraw sys type System File and xraw inf type Setup...

Страница 49: ...FPGA Connectivity TRD Click Finish to close the InstallShield Wizard Figure 44 6 Load recompiled drivers To install the recompiled drivers run x_v6_trd_setup exe again The InstallShield Wizard for the...

Страница 50: ...odifying the Virtex 6 FPGA Targeted Reference Design of this install process the driver and GUI files are copied to the C Program Files Xilinx Inc Virtex6 folder Figure 45 X Ref Target Figure 45 Figur...

Страница 51: ...s xrawdata and xaui are loaded manually through the Found New Hardware Wizard To load the recompiled xdma driver select Install from a list or specific location and click Next Browse and choose v6_pci...

Страница 52: ...664 v1 4 July 6 2011 Modifying the Virtex 6 FPGA Targeted Reference Design To load the recompiled xrawdata driver select Install from a list or specific location and click Next Browse and choose X Ref...

Страница 53: ...Modifying the Virtex 6 FPGA Targeted Reference Design v6_pcie_10Gdma_ddr3_xaui_axi compiled_drivers xrawdata and click Next The Xilinx Raw Data driver is installed Click Finish to load the next driver...

Страница 54: ...erence Design To load the recompiled xaui driver select Install from a list or specific location and click Next Browse and choose v6_pcie_10Gdma_ddr3_xaui_axi compiled_drivers xaui and click Next The...

Страница 55: ...ep 18 page 32 in Hardware Demonstration Setup Instructions to completely verify the modified settings 9 Follow step 1 page 33 through step 4 page 36 in Evaluating the Virtex 6 FPGA Connectivity TRD to...

Страница 56: ...the device driver and launches the Performance Monitor application c Click Run in Terminal to proceed 4 Follow step 16 page 30 through step 18 page 32 in Hardware Demonstration Setup Instructions to c...

Страница 57: ...col User Guide Table 1 Design File Organization for the Virtex 6 FPGA Connectivity TRD Module Name Source Files Directories LogiCORE IP Connectivity TRD Source Top Level Module Virtex 6 FPGA Connectiv...

Страница 58: ...cture X Ref Target Figure 52 Figure 52 Design Module for PCI Express X Ref Target Figure 53 Figure 53 Design FIles for PCI Express x4 PCIe Link 5 0 Gb s or x8 PCIe Link 2 5 Gb s 64 bit AXI4 Stream Int...

Страница 59: ...structure X Ref Target Figure 54 Figure 54 Packet DMA Design Module X Ref Target Figure 55 Figure 55 Packet DMA Design FIles UG664_18_051911 Packet DMA C2S S2C C2S S2C 64 bit AXI4 Stream Basic Interf...

Страница 60: ...rtual FIFO and Memory Controller Block Design Module X Ref Target Figure 57 Figure 57 Multiport Virtual FIFO and Memory Controller Design FIles UG664_20_060110 Native Interface of DDR3 Memory Controll...

Страница 61: ...ows the XAUI design module Figure 59 shows the design file structure X Ref Target Figure 58 Figure 58 XAUI Design Module X Ref Target Figure 59 Figure 59 XAUI Design FIles UG664_22_060110 XAUI GTX Tra...

Страница 62: ...I X Ref Target Figure 60 Figure 60 Software Device Driver and Software Application GUI Design Module UG664_24_052810 x4 PCIe Link 5 0 Gb s or x8 PCIe Link 2 5 Gb s Base DMA Driver Raw Data Driver XAUI...

Страница 63: ...ion version of the Northwest Logic PCIe Packet DMA IP Core This 64 bit DMA IP core is optimized for the Virtex 6 FPGA architecture The DMA design deliverables are Simulation model Hardware evaluation...

Страница 64: ...sceivers running at 3 125 Gb s The IBERT v2 0 reference design available through the CORE Generator tool for IP delivery The design also includes a pseudo random bit sequence PRBS pattern generator an...

Страница 65: ...s S1 and S2 to load the IBERT design from the CompactFlash see Figure 63 where X Don t care 1 ON 0 OFF a Set S1 to 1110 Position 4 is the most significant bit and Position 1 is the least significant b...

Страница 66: ...le to the USB JTAG connector on the ML605 board b Connect the other end of this cable to the PC system 5 Board Setup IV Use the SMA cables to loop back the transceiver channel pinned to the SMA on the...

Страница 67: ...PGA IBERT Reference Design b Connect J6 to J8 see Figure 66 c Connect J3 to J9 see Figure 67 X Ref Target Figure 66 Figure 66 Configuring the SMA Transceiver Channel with External Loopback II X Ref Ta...

Страница 68: ...ee Figure 68 e Connect J11 to J12 with a SATA loopback cable included in the Virtex 6 FPGA Connectivity Kit see Figure 69 X Ref Target Figure 68 Figure 68 Configuring the SMA Transceiver Channel with...

Страница 69: ...FPGA IBERT Reference Design 6 Board Setup V Connect the power connector a Using the included power supply connect the power supply connector to the ML605 board as shown in Figure 70 b The power switc...

Страница 70: ...e IBERT Reference Design files are provided on a USB flash drive delivered as a part of the kit Copy the contents of the included USB flash drive a Insert the USB flash drive into a USB connector of t...

Страница 71: ...Analyzer b Click on Open Cable Button as shown in Figure 72 10 Open the ChipScope Pro Analyzer project see Figure 73 a Click File Open Project b Navigate to the ML605_FMC_XM104_Ibert_Reference_Design...

Страница 72: ...esign through the GUI see Figure 75 GTX0_113 FMC Daughter Card connector DP3 SATA2 Host Channel GTX1_113 FMC Daughter Card connector DP2 SATA1 Host Channel GTX2_113 FMC Daughter Card connector DP1 SMA...

Страница 73: ...els as None no internal loopback The GTX2_113 and GTX3_113 transceiver channels have been looped on external loopback through an SMA cable Select the loopback mode for these transceiver channels as No...

Страница 74: ...r count should be 0 Congratulations The IBERT reference design for the Virtex 6 FPGA Connectivity Kit has been set up and the pre built demo that uses the GTX transceivers running at 3 125 Gb s has be...

Страница 75: ...ption General Developer Name Xilinx Target devices stepping level ES production speed grades XC6VLX240T 1 FF1156 Source code provided Y for custom logic only Source code format Verilog Design uses cod...

Страница 76: ...or neglect or default of Customer For any breach by Xilinx of this limited warranty the exclusive remedy of Customer and the sole liability of Xilinx shall be at the option of Xilinx to replace or rep...

Страница 77: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Xilinx DK V6 CONN G J DK V6 CONN G...

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