Xilinx Virtex-6 FPGA, Руководство по началу работы

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56 www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Modifying the Virtex-6 FPGA Targeted Reference Design
Linux Driver
To make software design changes, follow these steps:
1. Use the PC system on which the ML605 evaluation board is installed.
2. Copy the contents of the included USB stick into a local directory on this machine:
a. Navigate to the
v6_pcie_10Gdma_ddr3_xaui_axi/linux_driver/xdma/
directory.
b. Edit the
xdma_base.c
file.
c. Search for this string: #define PCI_VENDOR_ID_DMA .
- Change the alphanumeric value
10EE
found on this line, with the vendor ID
assigned to the user’s company by PCI-SIG (e.g., the vendor ID for Xilinx is
10EE
). Change this value to
19AA
.
- Save the changes and exit.
3. Load the driver and launch the Performance Monitor application:
a. Navigate to the
v6_pcie_dma_ddr3_xaui_axi
folder.
b. Double-click v6_trd_lin_quickstart .
This step builds kernel objects, loads the device driver, and launches the
Performance Monitor application.
c. Click
Run in Terminal
to proceed.
4. Follow step 16, page 30 through step 18, page 32 in Hardware Demonstration Setup
Instructions to completely verify the modified settings.
5. Follow step 1, page 33 through step 4, page 36 in Evaluating the Virtex-6 FPGA
Connectivity TRD to evaluate the performance for the modified design.
6. Review the system status.
Click
System Status
to review:
• PCIe link status, Vendor ID, and Device ID information.
• The vendor ID displayed on this screen should be equal to
19AA
, corresponding
to the hardware change that was performed.
Congratulations! The Virtex-6 FPGA Connectivity Kit using the connectivity TRD has been
fully set up, and the system performance has been evaluated. The Xilinx design flow has
been reviewed for modifying the connectivity TRD. This design includes the built-in
integrated block for PCI Express (4-lane, 5 GT/s configuration for PCI Express v2.0), XAUI
LogiCORE IP, a Virtual FIFO memory controller designed to interface to the onboard
DDR3 SODIMM device, and a third-party DMA controller for PCI Express.